Bit Interleaved Low Voltage SRAM Stabilization
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Solution Overview
Problem
Static random access memory (SRAM) devices, particularly 8-T SRAM cells, face challenges in maintaining reliability at low voltages due to increased susceptibility to soft errors and the half-select disturb problem, which complicates bit interleaving and error correction, especially as process technology scales.
Innovation Solution
The implementation of deeply depleted channel (DDC) transistors with a highly doped screening region and a threshold voltage set region, allowing for enhanced body biasing and reduced dopant variation, stabilizes half-selected SRAM cells and enables bit interleaving while operating at near or sub-threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit interleaving is implemented to reduce soft error susceptibility, then reliability is improved, but half-select disturb problem increases and device complexity increases
Solution Approach 1:
The SRAM array is divided into multiple interleaved groups where bits of the same data word are distributed across different physical locations. This segmentation allows write operations to be performed on selected groups without affecting other groups, thereby reducing half-select disturb while maintaining reliability benefits of bit interleaving.
Solution Approach 2:
A write word line enable signal is introduced as an intermediary control mechanism. This signal selectively enables write operations only for the intended SRAM cells while keeping other cells in a stable state, preventing half-select disturb from propagating and allowing the system to tolerate the complexity of bit interleaved structures.
2Stability of the object's composition
If 8-T SRAM design is used to maintain read robustness at low voltages, then read stability is improved, but device complexity increases
Solution Approach 1:
The 8-T SRAM cell structure is designed to perform multiple functions: it provides separate read and write ports for independent optimization, maintains stability under half-select conditions through its symmetric structure, and enables operation at low voltages. The additional transistors are arranged to create functional redundancy that serves multiple purposes simultaneously.
3Use of energy by moving object
If low operating voltages are used to reduce power consumption, then energy efficiency is improved, but reliability deteriorates due to increased soft error susceptibility
Solution Approach 1:
The SRAM cell design parameters are optimized for low voltage operation by adjusting transistor sizing, doping concentrations, and interconnect dimensions. These parameter changes enable the cell to maintain stable operation and error detection capability at reduced voltages, balancing power consumption and reliability.
Data Source
AI summary
A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.