Semiconductor Memory Device with Periodic State Inversion
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Solution Overview
Problem
Semiconductor memory devices using magnetoresistive elements face challenges in reducing write current while maintaining thermal stability and service life, especially when subjected to varying application environments, due to the limitations in reducing film thickness and damping constant, which affects the magnetoresistive ratio and stress applied to the MTJ elements.
Innovation Solution
A semiconductor memory device with a memory cell array that switches between low-resistance and high-resistance states based on data, utilizing a timer circuit to generate pulses and flag cells to store allocation information, allowing for data write and read operations while preventing biased stress on magnetoresistive elements by periodically inverting data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the film thickness of the MgO barrier is reduced to lower resistance, then the resistance decreases, but the MTJ element is subjected to high-voltage stress which degrades service life
Solution Approach 1:
The patent applies periodic inversion of data states in memory cells to alternately switch between low-resistance and high-resistance states. This periodic action distributes the high-voltage stress exposure over time, preventing continuous stress on the same MTJ elements and thereby extending service life while maintaining the ability to use thin MgO barriers for low resistance
2Use of energy by moving object
If the volume of the free layer is reduced to lower write current, then the write current decreases, but thermal stability is degraded
Solution Approach 1:
The patent utilizes parameter changes in the magnetoresistive elements, specifically switching between parallel and anti-parallel magnetization states of the free layer relative to the pinned layer. By changing the magnetic state parameters rather than physically changing the free layer volume, the system achieves different resistance states for data storage without compromising thermal stability
3Area of stationary object
If the area of the MTJ element is reduced to minimize cell area, then the cell area decreases, but the magnetoresistive ratio and stress distribution become problematic
Solution Approach 1:
By implementing periodic state inversion, the patent ensures that no single MTJ element remains in the same resistance state continuously. This distributes the electrical stress and magnetoresistive ratio extremes across different elements over time, allowing smaller cell areas without compromising the service life of individual MTJ elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution extends the service life of memory cells by mitigating the impact of unbalanced application environments and allows for efficient data storage in both volatile and nonvolatile RAM applications, ensuring consistent performance across different usage conditions.
Implementation Method 1
a magnetoresistive element having a laminated structure obtained by sequentially laminating a lower electrode, fixed layer, nonmagnetic layer, recording layer and upper electrode
Implementation Method 2
In a spin transfer torque writing type MRAM, inversion of magnetization occurs by causing a current to flow in a direction perpendicular to the film surface of the MTJ element to transfer spins into the free layer
Implementation Method 3
a film of polysilicon magnesium oxide (MgO) oriented in a (001) plane as a tunnel barrier layer of the MTJ element is disposed between films of polysilicon CoFeB oriented in a (001) plane so as to cause MgO to act as a spin filter
Implementation Method 4
a magnetic random access memory (MRAM) utilizing a tunneling magnetoresistive (TMR) effect
Implementation Method 5
a timer circuit which generates a pulse at each preset time
Data Source
AI summary
A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.