3D Memory Channel Patterns With Localized Dopant Regions
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the high cost of fine pattern forming technology, while three-dimensional semiconductor memory devices face challenges in achieving optimal integration and performance.
Innovation Solution
A semiconductor memory device design featuring word lines, channel patterns, bit lines, and data storage elements with specific dopant regions and insulating structures, allowing for three-dimensional arrangement and enhanced integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to high cost of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction (third direction perpendicular to substrate), allowing higher integration without requiring finer lateral patterning. This dimensional change enables increased capacity while avoiding the high cost of advanced fine pattern forming technology.
2Productivity
If three-dimensional semiconductor memory devices are used, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple identical cell stacks arranged in arrays. Each stack contains vertically stacked components (bit lines, word lines, memory cells) that can be manufactured using repeated patterning and deposition cycles. This segmentation allows complex 3D structures to be built through modular, repeatable process steps rather than monolithic complex fabrication.
Solution Approach 2:
The patent employs preliminary patterning actions where mandrel structures and spacer structures are formed in advance to define the final channel and electrode patterns. These preliminary structures guide subsequent deposition and etching steps, simplifying the overall manufacturing process by breaking down complex pattern formation into sequential, manageable stages.
3Reliability
If dopant regions are optimized for performance, then device reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality variations within dopant regions by creating different dopant concentrations in different areas. Specifically, the second dopant region contains a high concentration region adjacent to the data storage element and a low concentration region adjacent to the channel region. This local differentiation optimizes device performance by providing strong doping where needed while maintaining appropriate electrical characteristics in other areas, without requiring uniformly high precision across the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design achieves higher integration and performance by optimizing the arrangement and doping of semiconductor components, reducing manufacturing costs and improving operational efficiency.
Implementation Method 1
Each of the channel patterns may include a first dopant region adjacent to the bit lines, a second dopant region adjacent to the data storage elements, and a channel region provided between the first and second dopant regions
Data Source
AI summary
A method of fabricating a semiconductor memory device includes forming a mold structure on a substrate, the mold structure including channel patterns, interlayer insulating patterns, and sacrificial patterns between the channel patterns and the interlayer insulating patterns, forming a first trench penetrating the mold structure, forming horizontal regions between the channel patterns and the interlayer insulating patterns by removing portions of the sacrificial patterns, performing a first doping process to form low concentration regions in a portion of each of the channel patterns, which portion is exposed to the horizontal regions; forming spacer insulating patterns in the horizontal regions to surround each portion of the channel patterns, and performing a second doping process to form a high concentration region in a portion of each low concentration dopant region.