Fault-Tolerant Memory System Using Dynamic Data Mapping
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Solution Overview
Problem
Conventional methods for dealing with faulty memory cells in integrated circuits are costly and impractical, failing to provide effective fault tolerance in memory circuits.
Innovation Solution
A fault-tolerant memory system is implemented using a fault register and fault mitigation control module to detect and mitigate faulty memory cells by reconfiguring memory access, allowing the system to operate satisfactorily even with a high number of faulty cells by zoning memory into sensitivity zones and dynamically adjusting data mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to deal with faulty memory cells, then memory reliability is improved, but device complexity and cost increase significantly
Solution Approach 1:
The memory array is divided into multiple zones, each with its own fault register and sensitivity coefficient. This segmentation allows independent fault management for each zone, reducing the complexity of managing faults across the entire memory array while maintaining reliability.
Solution Approach 2:
Fault registers are pre-configured with sensitivity coefficients during manufacturing or initialization. This preliminary action stores fault information in advance, allowing the system to quickly retrieve and apply appropriate sensitivity coefficients without complex real-time analysis, thereby improving reliability while keeping the system simple.
2Reliability
If redundant memory cells are added to achieve fault tolerance, then memory reliability is improved, but manufacturing cost and device area increase
Solution Approach 1:
Instead of adding redundant physical memory cells, the invention changes the operational parameters by introducing sensitivity coefficients that adjust how data is read from memory cells based on their fault status. This parameter-based approach achieves fault tolerance without increasing manufacturing cost or device area.
3Reliability
If sensitivity coefficients are used to adjust data reading, then fault tolerance is improved, but power consumption increases
Solution Approach 1:
The system applies sensitivity coefficients selectively based on the fault status of each memory zone. Rather than continuously adjusting all memory operations, the system only modifies reading operations for zones with detected faults, achieving fault tolerance while minimizing unnecessary power consumption from constant adjustments.
4Reliability
If memory is zoned into sensitivity zones with different coefficients, then fault mitigation is improved, but device complexity increases
Solution Approach 1:
The fault register serves multiple functions: it stores fault information, holds sensitivity coefficients, and enables zone identification. This multi-functionality allows the system to achieve sophisticated fault mitigation through zoning without proportionally increasing device complexity, as the same hardware structure performs multiple roles.
Data Source
AI summary
A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.