Distributed Write Driver Current Control for Memory Line Resistance
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Solution Overview
Problem
Existing memory devices face issues with parasitic resistances in memory lines leading to uneven write voltages and potential half-biasing of memory cells due to varying distances from the write driver, necessitating high supply voltages that can cause unintended activation of non-targeted cells.
Innovation Solution
A write driver system that adjusts current and voltage pulse durations based on the distance of memory cells from the driver, using sets of transistors with varying widths or activation times to ensure proper access and avoid half-biasing, thereby accounting for parasitic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a high supply voltage is used to access distant memory cells, then the write operation can reach far memory cells, but near memory cells may be unintentionally activated (half-biasing)
Solution Approach 1:
The patent applies local quality by providing different current amounts to different memory cells based on their distance from the write driver. Near memory cells receive a first current amount while distant memory cells receive a second, larger current amount. This localized differentiation ensures that each memory cell receives the appropriate current for reliable access without causing unintended activation of cells that do not require the higher current.
2Power
If a larger current is provided to distant memory cells, then the write operation can overcome parasitic resistance, but the write driver requires higher supply voltage
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting the current amount provided by the write driver based on the distance to the target memory cell. The system changes the electrical parameter (current) to match the specific requirements of each memory cell location, allowing distant cells to receive higher current to overcome parasitic resistance while near cells receive lower current, thereby avoiding the need for a uniformly high supply voltage across all operations.
3Ease of operation
If the same current is provided to all memory cells, then the write driver operation is simplified, but memory cells at different distances experience different effective voltages due to parasitic resistance
Solution Approach 1:
The patent applies local quality by differentiating the current provision based on memory cell location. Instead of uniform treatment, the system provides a first current amount to near memory cells and a second, larger current amount to distant memory cells. This localized adaptation compensates for the varying parasitic resistance effects, ensuring that all memory cells experience consistent effective write voltages despite their different distances from the write driver.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively accesses memory cells at varying distances without requiring increased supply voltages, preventing half-biasing and ensuring consistent write operations across the memory array.
Implementation Method 1
mitigate the problems arising from the parasitic resistances of the memory lines of the memory device
Implementation Method 2
the memory cell is typically first activated by sending a current on the word line to which it is connected, which causes an activation voltage to be applied to the memory cell
Data Source
AI summary
The disclosed technology relates to a write driver and a method for operating the write driver for a memory device. The write driver is connected to a memory line of the memory device. Multiple memory cells of the memory device are connected to the memory line at different distances from the write driver. The operating method comprises controlling the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells, and controlling the write driver to provide a larger amount of current for accessing a second memory cell of the memory cells. Thereby, the first memory cell is connected to the memory line at a smaller distance to the write driver than the second memory cell.