STT-MRAM Reference Cell Control Circuit for Power Reduction

Solution Overview

Problem

The existing methods for generating a reference potential in spin transfer torque magnetoresistive random access memory (STT-MRAM) devices lead to increased power consumption and chip costs due to the need for parallel refresh operations with write operations, causing unintended logic inversion and requiring periodic refresh operations.

Innovation Solution

A control circuit that separates a second reference element from a sense amplifier during data read operations, using a first reference element connected to the sense amplifier to generate a reference potential, thereby reducing power consumption and chip costs by performing refresh operations only on unused reference cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operation is performed on reference cell in parallel with write operation to memory cell, then reliability of reference cell is improved, but power consumption increases and chip cost increases due to peak current increase

Engineering Contradiction:

Improvereference cell data reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the reference cell operation into two distinct phases: a first period where the reference cell is connected to the sense amplifier for data reading, and a second period where the reference cell is disconnected from the sense amplifier for refresh operation. This temporal segmentation allows the reference cell to be refreshed without simultaneously driving the sense amplifier, thereby eliminating the peak current surge that would occur if both operations occurred in parallel, while still maintaining data reliability through periodic refresh.

Inventive Principle:

Principle #1Segmentation

2Reliability

If refresh operation is performed on reference cell in parallel with write operation to memory cell, then reference cell is kept updated, but chip cost increases due to peak current increase

Engineering Contradiction:

Improvereference cell data reliabilityVSAvoidchip cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the reference cell operation into two distinct phases: a first period where the reference cell is connected to the sense amplifier for data reading, and a second period where the reference cell is disconnected from the sense amplifier for refresh operation. This temporal segmentation allows the reference cell to be refreshed without simultaneously driving the sense amplifier, thereby eliminating the peak current surge that would occur if both operations occurred in parallel, while still maintaining data reliability through periodic refresh.

Inventive Principle:

Principle #1Segmentation

3Ease of operation

If reference cell is connected to sense amplifier continuously, then data readout is enabled, but reference cell data may be unintentionally inverted

Engineering Contradiction:

Improvedata readout capabilityVSAvoidreference cell data integrity

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent implements periodic action by alternating between two operational states: during a first period, the reference cell is connected to the sense amplifier to enable data readout; during a second period, the reference cell is disconnected from the sense amplifier to prevent unintended inversion and allow refresh operations. This periodic switching ensures that the reference cell is both accessible for reading when needed and protected from data corruption during intervals when it is isolated, maintaining data integrity while preserving readout capability.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS10971197B2Control circuit, semiconductor memory device, information processing device, and control method

Publication Date: 2021.04.06 SONY SEMICON SOLUTIONS CORP

AI summary

To provide a control circuit capable of reliably generating a reference potential while suppressing increase in power consumption and cost. Provided is a control circuit that performs control to separate from a sense amplifier a second reference element set to a predetermined resistance state, which is different from a first reference element set to a predetermined resistance state and connected to the sense amplifier in generating a reference potential used for data read through the sense amplifier from a memory cell.