Ferroelectric Memory Voltage Control for Interference Suppression
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Solution Overview
Problem
Conventional ferroelectric memories suffer from high refresh frequency due to interference voltages affecting unselected memory cells, which reduces the information read window and necessitates frequent refresh operations, impairing their implementability.
Innovation Solution
A control method and apparatus that reduces interference voltages by applying specific voltage differences between selected and unselected word and plate lines during active phases, maintaining a reduced voltage difference across unselected memory cells to prevent polarization changes, thereby enhancing the read window and reducing refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage control is used during memory access, then the ferroelectric capacitor can be accessed, but interference voltage causes high refresh frequency
Solution Approach 1:
The patent applies different voltage levels to selected and unselected plate lines during memory access operations. Specifically, when accessing a memory cell, the selected plate line receives a voltage (e.g., Vpp) while unselected plate lines receive a different voltage (e.g., 0V or a reduced voltage). This parameter change in voltage control prevents polarization changes in unselected memory cells, reducing interference and lowering refresh frequency requirements while maintaining data retention reliability.
2Ease of operation
If voltage is applied to access memory cells, then data can be read/written, but interference voltage reduces the information read window
Solution Approach 1:
The patent implements local quality control by applying voltage selectively to specific plate lines based on their selection status. The selected plate line receives the full access voltage to enable read/write operations, while unselected plate lines receive reduced or zero voltage to minimize interference. This localized voltage application ensures that only the targeted memory cell experiences the full voltage swing needed for operation, preserving the information read window for other cells.
3Productivity
If high voltage is applied to the selected plate line for memory access, then the target memory cell can be accessed, but unselected memory cells experience interference
Solution Approach 1:
The patent segments the plate line control into separate voltage domains for selected and unselected lines. Instead of applying voltage uniformly across all plate lines, the system divides them into groups: the selected plate line receives high voltage for rapid memory access, while unselected plate lines are maintained at low or zero voltage. This segmentation isolates the high-voltage effect to only the target memory cell, enabling fast access without creating interference voltages in other cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the performance of ferroelectric memories by increasing the resistance to read/write interference, maintaining the information read window, and reducing the refresh frequency, thus enhancing their implementability.
Implementation Method 1
the change of the charge on the BL is mainly caused by a polarization charge released by a ferroelectric capacitor due to polarity switching when the ferroelectric capacitor of the memory cell is under an action of a voltage that exceeds a coercive field voltage Vc
Data Source
AI summary
The apparatus includes transistors and a memory cell array. Memory cells located in a same column are coupled to a same transistor and a same word line, the transistors are coupled to a bit line, and memory cells located in a same row are coupled to a same plate line. The method includes turning on a transistor coupled to an unselected word line, applying a first voltage V1 to a bit line and applying a second voltage V2 to an unselected plate line, and using a selected word line, turning on a transistor coupled to the selected word line, applying a third voltage V3 to the bit line, and applying a fourth voltage V4 to a selected plate line, |V4−V3|=Vw, |V4−V1|<½Vw, |V3−V2|<½Vw.