Timing Signal Correction for 3D IC Voltage Domain Shifts
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Solution Overview
Problem
In the electronics industry, there is a challenge in maintaining precise timing signals across interfaces between dies with independent voltage domains, leading to timing shifts and duty cycle errors, which affect the performance and efficiency of 3D integrated circuits.
Innovation Solution
The implementation of a method that uses timing compare circuitry to calculate a correction value based on timing deltas, allowing adjustments to subsequent timing signals and reference voltage settings, thereby correcting for voltage-induced timing shifts and duty cycle errors across interfaces with independent voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If timing signals are transmitted across interfaces between dies with independent voltage domains, then data communication between stacked dies is enabled, but timing shifts and duty cycle errors occur due to voltage variations
Solution Approach 1:
The patent implements a feedback mechanism where timing compare circuitry continuously monitors the timing of received signals and generates timing delta values that indicate deviations from expected timing. These timing deltas are fed back to adjust the timing of subsequent signals, creating a closed-loop system that compensates for voltage-induced timing shifts and maintains precise timing communication across dies with independent voltage domains
Solution Approach 2:
The patent dynamically adjusts timing parameters based on observed timing deltas. By changing the timing of subsequent signals according to measured deviations, the system adapts to voltage variations in real-time, maintaining timing precision despite changes in voltage domain conditions across the stacked die interface
2Measurement precision
If large and complex duty cycle measurement circuits are implemented to correct timing shifts, then timing precision is improved, but device size and power consumption increase
Solution Approach 1:
The patent extracts only the essential timing information from received signals using simple timing compare circuitry that generates timing delta values. Rather than implementing complex full-duty-cycle measurement circuits, the invention isolates and corrects only the timing deviation component, significantly reducing circuit complexity while maintaining timing precision
Solution Approach 2:
The patent uses simplified timing compare circuitry that creates a temporal copy or representation of the received signal's timing characteristics. This temporal copy in the form of timing delta values is sufficient for correction purposes without requiring full replication of complex measurement functionality, reducing overall circuit complexity
3Measurement precision
If timing correction mechanisms are added to maintain timing precision, then timing signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing correction function into distinct modular components: timing compare circuitry that measures timing deltas, correction logic that processes these deltas, and adjustment mechanisms that apply corrections to subsequent signals. This segmentation allows each component to be optimized independently and simplifies the overall design while maintaining timing accuracy
Data Source
AI summary
Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to a subsequent timing signal, adjustment to a reference voltage setting associated with the subsequent timing signal, other adjustments, or combinations thereof. Additional apparatus, systems, and methods are disclosed.