Reversible Polarity Decoders for 3D Passive Memory Arrays
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Solution Overview
Problem
In three-dimensional memory technology, the high voltages required for programming and erasing passive element memory cells pose challenges as they do not scale well with decreasing word line and bit line pitches, leading to compatibility issues with smaller array line pitches and increased leakage current in unselected memory cells.
Innovation Solution
A passive element memory array incorporating reversible polarity word line and bit line decoders that bias selected lines at different voltages than unselected lines, reducing the voltage requirements for decoder circuits and minimizing leakage current by keeping unselected memory cells in a reverse bias mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage (6-8V for programming, 10-14V for erase) is applied to passive element memory cells, then programming and erasing can be achieved, but the voltage requirements do not scale well as word line and bit line pitch decreases
Solution Approach 1:
The patent introduces a time dimension by implementing reversible polarity decoders that switch between forward and reverse bias modes. This allows the same physical structure to serve different voltage requirements at different times, enabling high voltage operation when needed while maintaining compatibility with small pitch dimensions through standardized decoder structures.
Solution Approach 2:
The decoder polarity is changed as a controllable parameter. By switching the decoder between forward bias mode (for programming) and reverse bias mode (for erase), the voltage characteristics are dynamically adjusted to match the operational requirements, allowing the same hardware to support both high-voltage operations and small-pitch compatibility.
2Reliability
If high voltage transistors are used in word line and bit line decoders to support high voltage operations, then programming and erasing can be performed, but the transistors do not scale well as memory cell word line and bit line pitch decreases
Solution Approach 1:
The decoder circuit transitions from a static high-voltage design to a dynamic reversible polarity design. The same decoder structure can operate in forward bias mode requiring high voltage transistors, or switch to reverse bias mode where standard transistors suffice, allowing the circuit to adapt its voltage requirements to the operational mode and scale accordingly.
Solution Approach 2:
The reversible polarity decoder serves multiple functions: it can perform both forward bias programming and reverse bias erase operations using the same physical structure. This multi-functionality eliminates the need for separate high-voltage and low-voltage decoder circuits, reducing overall device complexity while maintaining high voltage support capability when needed.
3Reliability
If selected word lines and bit lines are biased at high voltage simultaneously, then memory cell programming can be achieved, but leakage current increases in unselected memory cells
Solution Approach 1:
The patent employs reverse bias mode for erase operations where the polarity is inverted compared to programming. During reverse bias mode, previously selected lines that were at high voltage are now reversed, placing unselected cells in a reverse bias state that minimizes leakage current, while the selected cell receives the necessary voltage for erase operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient programming and erasing of memory cells with reduced voltage requirements and minimized leakage current, enabling larger block sizes with minimal power dissipation and improved compatibility with smaller array pitches.
Implementation Method 1
biasing, in a first mode of operation, selected word lines at a lower voltage than unselected word lines, and selected bit lines at a higher voltage than unselected bit lines, and for biasing, in a second mode of operation, selected word lines at a higher voltage than unselected word lines, and selected bit lines at a lower voltage than unselected bit lines
Implementation Method 2
The word line decoder circuit sources a current through a selected passive element memory cell in one of the two modes of operation, and sinks a current through the selected passive element memory cell in the other of the two modes of operation
Implementation Method 3
minimizing leakage current by keeping unselected memory cells in a reverse bias mode
Data Source
AI summary
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.