Memory Command Input Scheme Using Dual Clock Edges
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Solution Overview
Problem
Existing memory devices face challenges in efficiently handling high-capacity and high-bandwidth data processing, particularly in the context of multichannel interfaces, requiring an improved command input scheme to enhance operational efficiency and speed.
Innovation Solution
A memory device and method that allows for the transmission and reception of commands at both the rising and falling edges of a clock signal, enabling faster and more efficient operation by allowing commands like pre-charge to be received with minimal delay, thereby optimizing memory access and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are received only at rising edge of clock signal, then device complexity is reduced, but productivity is limited
Solution Approach 1:
The patent applies periodic action by enabling command reception at both rising and falling edges of the clock signal. This doubles the frequency of command processing opportunities without requiring a fundamentally different input mechanism, thereby improving productivity while maintaining relatively simple device architecture.
Solution Approach 2:
The patent implements dynamics by making the command reception capability adaptive to clock signal edges. The memory device dynamically accepts commands based on clock edge detection (rising or falling), allowing flexible timing optimization without increasing structural complexity.
2Loss of time
If pre-charge command is received with minimal delay, then loss of time is reduced, but reliability may be affected
Solution Approach 1:
The patent applies preliminary action by preparing the memory device to accept pre-charge commands at any clock edge. This advance preparation allows the device to immediately process pre-charge commands when received, minimizing latency while maintaining execution reliability through pre-configured command recognition circuits.
Solution Approach 2:
The patent implements feedback mechanisms to verify command reception and execution status. The control logic monitors clock edges and command signals, providing feedback validation that ensures reliable command execution even with minimal delay between command issuance and processing.
3Productivity
If continuous memory access operations are enabled, then productivity increases, but loss of time between operations increases
Solution Approach 1:
The patent applies continuity of useful action by enabling command reception at both rising and falling clock edges. This allows overlapping command processing and memory operations to occur more continuously, reducing idle time between operations and increasing overall throughput without requiring additional hardware resources.
Data Source
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AI summary
Described is a method of operating a memory device including row pins and column pins. The method includes receiving a first active command through the row pins during a first one and a half cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first one cycle of the clock signal, receiving a first pre-charge command through the row pins during a first half cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second one and a half cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second one cycle of the clock signal, and receiving a second pre-charge command through the row pins during a second half cycle of the clock signal corresponding to a falling edge of the clock signal.