SRAM Latch Circuit with Selection Transistors for Write-Read Balance
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Solution Overview
Problem
Existing SRAM designs face challenges in achieving both high write capacity and read stability without increasing the width/length ratio of pull down transistors, which can lead to area penalties.
Innovation Solution
The introduction of selection transistors coupled to pull up transistors in SRAM cells, allowing decoupling during write operations to reduce the driving ability required of access transistors, and maintaining a favorable beta ratio for pull down transistors to ensure read stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width/length ratio of access transistors is increased to improve write capacity, then write capacity is improved, but the beta ratio deteriorates and read stability is compromised
Solution Approach 1:
The latch circuit is segmented by introducing selection transistors that can decouple the pull-up transistors from the storage nodes during write operations. This segmentation allows independent control of write and read paths, enabling the access transistors to have sufficient driving ability for writing without requiring excessively large width/length ratios that would harm read stability.
Solution Approach 2:
The selection transistors are dynamically controlled to be switched off during write operations and switched on during read operations. This dynamic switching allows the circuit to adapt its configuration based on the operation type, enabling optimal performance for both writing and reading without permanent structural compromises.
2Reliability
If the width/length ratio of pull down transistors is increased to improve read stability, then read stability is improved, but area penalty increases
Solution Approach 1:
By segmenting the latch circuit with selection transistors, the patent eliminates the need to increase pull-down transistor size for read stability. The selection transistors isolate the pull-up transistors during writes, preventing the need for oversized access transistors, which in turn allows pull-down transistors to maintain normal dimensions while still ensuring read stability.
Solution Approach 2:
The selection transistors act as intermediaries between the pull-up transistors and the storage nodes. During write operations, these intermediaries are switched off to prevent the pull-up transistors from interfering with the write process, thereby eliminating the need to oversize other transistors and avoiding area penalties.
3Productivity
If the width/length ratio of access transistors is increased to improve write capacity, then write capacity is improved, but transistor area increases
Solution Approach 1:
The introduction of selection transistors segments the write path from the read path, allowing the access transistors to have moderate dimensions. The selection transistors compensate for the reduced access transistor driving ability by actively disabling the pull-up transistors during writes, thus achieving good write capacity without area penalties.
Solution Approach 2:
The selection transistors serve as intermediaries that enable write operations even when access transistors have reduced dimensions. By controlling the selection transistors to switch off the pull-up path during writes, the system achieves effective write capability without requiring large access transistor areas.
Data Source
AI summary
A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.