Semiconductor Memory Repair Control Signal Logic
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Solution Overview
Problem
Semiconductor devices often malfunction due to defective memory cells, leading to inefficient production yield as whole devices are discarded instead of being repaired, and existing post-package repair methods can result in unintentional entry into repair mode causing malfunctions.
Innovation Solution
A semiconductor system with a memory controller and memory that determines whether to enable a control signal for block mode entry signals, entering a repair mode based on specific addresses and commands, and blocking entry to the repair mode during enabling sections of the control signal, preventing unintentional repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If post-package repair operation is enabled to replace defective memory cells, then production yield is improved, but unintentional entry to repair mode may cause device malfunction
Solution Approach 1:
A control signal generation block is introduced as an intermediary component that mediates between external inputs and the repair mode entry. This block generates a control signal that must be properly asserted before repair mode can be entered, preventing accidental or unintended mode transitions while allowing legitimate repair operations to proceed
2Ease of repair
If repair mode entry is allowed based on address and command signals, then defective cells can be repaired, but false entry due to signal interference may occur
Solution Approach 1:
The control signal generation block performs preliminary validation before allowing repair mode entry. It checks whether the block mode entry signal is properly asserted before responding to address and command signals that would otherwise trigger repair mode, thereby preemptively preventing false entry caused by signal interference or noise
Data Source
AI summary
A semiconductor system includes: a memory controller; and a memory which determines whether to enable a control signal in response to block mode entry signals applied from the memory controller, enters a repair mode in response to a first address and a first command applied from the memory controller, and blocks an entry to the repair mode during an enabling section of the control signal.