Semiconductor Memory Address Decoder Failure Detection
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Solution Overview
Problem
Current fault detection methods for address decoders in semiconductor devices, such as using ECC circuits, have limited detection capability for unknown data and require complex multiple data readings, making them inefficient for accurate failure detection.
Innovation Solution
A semiconductor device with a detection circuit that uses row and column encoders to encode address information and compare it with input address information, allowing for simple and accurate detection of failures in row and column address decoders by identifying anomalies in the encoded signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ECC circuits are used for fault detection, then detection capability for known errors is improved, but detection accuracy for unknown data remains low and device complexity increases
Solution Approach 1:
The patent creates encoded copies of address information through row and column encoders. These encoded versions are then compared with the original address information to detect decoder failures. This copying approach allows detection without requiring complex ECC circuits or multiple data reading operations, thereby improving detection accuracy while maintaining simple circuitry.
2Measurement precision
If multiple data readings are performed to improve detection accuracy, then detection capability is enhanced, but operational complexity and time consumption increase
Solution Approach 1:
The patent performs encoding of address information in advance during normal read/write operations. The encoders continuously generate encoded versions of row and column addresses, which are then compared with the original address information. This preliminary encoding action enables immediate detection of decoder failures without requiring additional multiple reading operations, thus improving detection accuracy while maintaining simple operation.
3Measurement precision
If address information is encoded and compared for failure detection, then detection accuracy for decoder failures is improved, but circuit complexity increases
Solution Approach 1:
The patent divides the address decoding process into separate row and column components, each with its own encoder. By segmenting the detection function into independent row and column encoder-comparator units, the system achieves comprehensive decoder failure detection while keeping each individual detection unit simple and modular, avoiding the need for complex overall circuitry.
Data Source
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AI summary
A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.