Quad-Channel DRAM Layout for High-Rate Capacity Doubling
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Solution Overview
Problem
Existing DRAM technologies face challenges in efficiently doubling memory capacity without excessively loading signal lines and maintaining high data rates when operating in dual-channel mode.
Innovation Solution
A quad-channel DRAM configuration that allows two channels to be inactivated, with the remaining active channels accessing the internal memory cores, and aligning DRAM devices on opposite sides of a substrate to appear as a single quad-channel device, enabling point-to-point signal routing and doubling memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two DRAM devices are mounted oppositely on a substrate to double memory capacity in dual-channel mode, then memory capacity is doubled, but signal lines become excessively loaded and data rates decrease
Solution Approach 1:
The patent divides the DRAM device into four independent channels, each with separate command/address and data buses. This segmentation allows the channels to operate independently, reducing signal interference and loading when devices are mounted oppositely on a substrate.
Solution Approach 2:
The patent transitions from traditional single-sided mounting to opposite-side mounting of DRAM devices on the substrate. This dimensional change in the physical arrangement allows for point-to-point signal routing between oppositely mounted devices, reducing signal loading while maintaining high data rates.
2Quantity of substance
If traditional DRAM mounting is used to double memory capacity, then capacity increases, but signal routing complexity increases and data rates are reduced
Solution Approach 1:
The four-channel architecture segments the memory device into independent channels with dedicated signal paths. Each channel has its own command/address and data buses, eliminating the need for complex shared signal routing when devices are mounted oppositely.
Solution Approach 2:
By mounting devices on opposite sides of the substrate and using point-to-point routing through the substrate, the patent simplifies signal routing compared to traditional same-side mounting. This dimensional approach reduces the number of signal branches and connections required.
Data Source
AI summary
A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.