Adaptive Clock Phase Control for LSI Power Noise Compensation
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Solution Overview
Problem
Conventional LSI circuits face challenges in maintaining optimal nominal signal delay due to variations in power supply voltage, leading to increased power consumption and design complexities.
Innovation Solution
The phase of the clock signal is controlled as a function of time variant changes in power supply voltage, using a phase adjustment circuit that varies the phase difference between the clock signal and the output clock signal, expressed by the equation φ(t) = -βT0 ∫(v(t) - v0) dt, with β being a constrained constant to limit phase changes and optimize power supply noise handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the nominal circuit delay time is increased to reduce power consumption and design costs, then power consumption decreases and design becomes easier, but the circuit becomes more sensitive to power supply noise causing clock cycle time variations
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable and adaptive rather than fixed. The phase adjustment circuit dynamically modifies the clock phase based on power supply voltage conditions, allowing the system to optimize between nominal delay time and clock cycle time stability. This dynamic adaptation resolves the contradiction by enabling the circuit to operate with higher nominal delay while compensating for noise effects through real-time phase adjustment.
Solution Approach 2:
The patent changes the phase parameter of the clock signal to compensate for power supply noise effects. By adjusting the phase shift introduced by the phase adjustment circuit, the system can maintain stable clock cycle times even when operating with higher nominal circuit delay times. This parameter change allows the circuit to achieve lower power consumption without sacrificing reliability.
2Reliability
If the nominal circuit delay time is decreased to maintain stability under power supply noise, then clock cycle time stability improves, but power consumption increases and design complexity increases
Solution Approach 1:
The phase adjustment circuit serves as an intermediary between the clock source and the digital circuit. It introduces a controllable phase shift that compensates for the effects of power supply noise on circuit delay. This intermediary component allows the system to maintain stable clock cycle times without requiring the nominal circuit delay to be minimized, thereby reducing power consumption and design complexity.
3Speed
If a higher nominal power supply voltage is used to reduce nominal circuit delay time, then nominal signal delay decreases, but power consumption increases
Solution Approach 1:
Instead of changing the power supply voltage to reduce signal delay, the patent changes the phase parameter of the clock signal. The phase adjustment circuit introduces a variable phase shift that effectively reduces the impact of circuit delay without requiring higher voltage operation. This approach achieves faster effective signal propagation while maintaining lower power consumption.
Data Source
AI summary
Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.