Single Output Arrangements TRIZ Cases

Phase rotators and a calibration controller align clock delays to calibrate driver slew rates and improve memory timing accuracy.

A two-stage delay circuit combines coarse and fine clock domains to raise microscope signal-delay resolution without excessive circuit complexity.

A DAC uses a PLL-derived reference voltage to create programmable intermediate clock phases without slew-rate-sensitive control circuitry.

Switch-pair bias control keeps signal crossing within clock overlap, producing uniform multi-phase clocks despite process and temperature variation.

Staggered clock outputs cut shared power-supply load spikes, improving waveform distortion without separate regulators or extra pins.

Consecutively coupled register cells and feedback nodes enable high-frequency non-overlapping clocks with stable startup and lower flicker noise.

Equal-length connection nets replace many buffer delays, improving clock tree balancing resolution while reducing layout area and cost.

Shared delay setting circuits recover clock delay faults across multiple macros while limiting memory and circuit size.

Two 180° phase-shifted clock paths and one-shot pulses generate an internal clock with lower duty cycle error and phase shift at high frequency.

A shared delay path replaces separate delay circuits to generate non-overlapping multi-phase clocks with lower area overhead and consistent timing.

A clock-based reference delay multiplied by an integer stabilizes delayed signal timing in semiconductor memory circuits.

Phase-difference measurement and delay adjustment eliminate intra-pair skew in differential signals, reducing jitter and bit errors.

Phase interpolation with complementary clock signals improves duty cycle correction accuracy, shortens lock time, and reduces temperature sensitivity.

Multiple differential pairs and selective activation generate 64 phase steps to align high-speed sampling windows with lower jitter and power.

Bias voltages tune delay circuits to correct clock duty ratio precisely despite transistor variation and short clock periods.

Fuse-stored frequency division values let each memory chip correct oscillator variation and generate accurate refresh request timing in one measurement.

A moving-sum and adaptive-threshold scheme corrects distorted square-wave duty cycles to 50% with simpler circuitry and lower current use.

Programmable delay insertion with a Muller gate and feedback masks propagation timing and keeps energy use more constant against attacks.

Encoded clock control generates down-converted, phase-shifted sampling clocks with lower jitter and better digital output accuracy at low power.

Feedback-controlled variable delays tune two-phase non-overlap clocks against voltage, temperature, and component variation.

Partial silicide on CMOS transistor gates adds resistance to tune signal delay in less chip area while preserving logic quality and rise/fall balance.

Multiple delayed clocks and held input samples let memory circuits choose latch timing automatically, improving high-frequency write accuracy.

Measures delay at different chain stages to detect true delay faults without extra flip-flops, improving fault judgment accuracy.

Clock phase is adjusted to power supply voltage changes, letting LSI circuits cut power while keeping clock cycle timing stable.

Distributed clock stages generate synchronized non-overlapping phases for pipelined ADCs while cutting power, area, and high-frequency timing overhead.