Clock Phase Splitter Layout for Low-Skew 180° Internal Clocks
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Solution Overview
Problem
Conventional phase splitters in memory integrated circuits experience significant skew between internal clock signals due to variations in process, voltage, and temperature (PVT), leading to errors in data output, as the number of inverters in different paths causes uneven delays.
Innovation Solution
The proposed phase splitter design includes a transfer unit, inverting unit, first and second buffers, and interpolating signal generators to generate internal clock signals with a 180° phase difference, with the buffers and interpolating signal generators having matching delays to minimize skew, and includes a transfer gate with PMOS and NMOS transistors to manage the clock signal delays effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of inverters in different paths is made equal, then the delay balance is improved, but the phase difference of 180° cannot be achieved
Solution Approach 1:
The patent divides the clock signal distribution into two separate paths: one path with an odd number of inverters (3 inverters) to generate the 180° phase-shifted clock signal, and another path with an even number of inverters (2 inverters) to generate the original phase clock signal. This segmentation allows each path to have equal delay while maintaining the required phase difference through the odd/even inverter count distinction.
Solution Approach 2:
The patent changes the parameter of inverter count from being equal in both paths to having an odd number in one path and an even number in the other path. This parameter change enables simultaneous achievement of equal delay (by balancing the total number of inverters to 5) and 180° phase difference (by having odd vs even inverter counts), resolving the technical contradiction.
2Reliability
If the number of inverters in the first path is increased to achieve 180° phase difference, then the phase accuracy is improved, but the delay skew increases
Solution Approach 1:
The patent segments the inverter distribution into two paths with different inverter counts (odd vs even) but equal total delay. The first path has 3 inverters and the second path has 2 inverters, with the fifth inverter strategically placed to balance the delays. This segmentation resolves the contradiction by allowing phase difference accuracy through odd/even distinction while minimizing delay skew through equal delay design.
3Loss of time
If the inverter delays are made equal in both paths, then the skew is reduced, but the 180° phase difference cannot be maintained
Solution Approach 1:
The patent changes the inverter count parameters from being equal (2 and 2) to having an odd number in one path (3) and an even number in the other (2), with the total inverted to 5. This parameter change enables the system to maintain equal delays (reducing skew) while achieving 180° phase difference through the odd/even inverter count distinction.
Data Source
AI summary
A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.