Two-Phase Clock Delay Control for Stable Non-Overlap Timing
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Solution Overview
Problem
Conventional clock signal generation apparatuses for discrete-time analog circuits face challenges in generating optimal non-overlap clock signals due to fluctuations in temperature, power supply voltage, and component variations, leading to potential circuit malfunction and increased power consumption.
Innovation Solution
A clock signal generation apparatus featuring variable delay devices, a non-overlap detector, and a control signal generation section that adjusts delay times based on detected non-overlap times to ensure optimal non-overlap periods, thereby preventing timing failures and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay elements are used to generate non-overlap timing, then non-overlap time is obtained, but the timing varies significantly due to power supply voltage fluctuations and temperature fluctuations
Solution Approach 1:
The patent implements a feedback mechanism where the actual non-overlap time is measured and used to adjust the delay element settings. A control signal generation section receives the measured non-overlap time and generates control signals to adjust the variable delay devices, creating a closed-loop system that compensates for environmental variations and maintains stable timing.
Solution Approach 2:
The patent employs variable delay devices whose delay characteristics can be dynamically adjusted based on operating conditions. Instead of using fixed delay elements, the system allows real-time modification of delay parameters to adapt to temperature and voltage changes, ensuring consistent non-overlap timing across different operating environments.
2Reliability
If non-overlap zone is increased to prevent malfunction, then reliability improves, but the H-level zones of clock timings become short requiring higher operation speed
Solution Approach 1:
The system dynamically adjusts the delay characteristics of the clock signal generation circuitry to optimize the balance between non-overlap zone duration and H-level zone duration. By making the delay elements variable and controllable, the system can adapt the timing parameters to achieve both adequate non-overlap protection and sufficient H-level duration for proper circuit operation.
Solution Approach 2:
The patent changes the delay parameters of the clock signal generation circuit based on measured actual non-overlap times. By adjusting delay element characteristics through control signals, the system optimizes the timing parameters to maintain reliable operation while maximizing the H-level zone duration, thereby reducing the required operation speed of downstream circuits.
3Reliability
If H-level zones are shortened to accommodate larger non-overlap time, then non-overlap reliability improves, but circuit components must operate at higher speed increasing power consumption
Solution Approach 1:
The system adjusts the delay parameters of the clock signal generation circuit to optimize the balance between non-overlap time accuracy and power consumption. By controlling the variable delay devices with feedback from actual non-overlap measurements, the system maintains reliable timing while maximizing H-level zone duration, thereby reducing the speed requirements and power consumption of downstream circuit components.
4Area of stationary object
If conventional delay elements are used, then circuit area is reduced, but timing precision deteriorates due to environmental fluctuations
Solution Approach 1:
The patent introduces a feedback mechanism where a non-overlap detection section measures the actual non-overlap time and provides this information to a control signal generation section. This closed-loop system compensates for timing variations caused by environmental factors, maintaining high measurement precision without requiring excessively large circuit area, as the feedback control efficiently corrects timing errors.
Data Source
AI summary
A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.