Adjustable Delay Cell for DDR RAM Signal Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed Double Data Rate (DDR) random access memory (RAM) requires precise adjustment of delay steps in delay line circuits to ensure accurate signal delay, which is challenging due to the need for smaller delay cell step sizes and increased complexity with more delay cells.
Innovation Solution
The implementation of an adjustable delay cell with a buffer and multiplexer that adjusts signal transmission speed in response to a control signal, allowing for variable delay steps by activating drivers and transistors based on control signal bits, enabling flexible delay control in delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of delay cells is increased to achieve smaller delay steps, then the delay precision is improved, but the device complexity increases
Solution Approach 1:
The delay cell employs dynamic control signals (UP, DOWN, CLEAR) to adjust the delay step size in real-time, allowing the circuit to adapt between coarse and fine delay adjustments without requiring additional fixed delay cells. This dynamic adjustment mechanism resolves the contradiction by providing variable precision without proportionally increasing device complexity.
Solution Approach 2:
The invention changes the operational parameters of the delay cell through control signals that modify the delay step size. By varying the delay step between a first value (coarse adjustment) and a second value (fine adjustment), the system achieves high precision delay control without needing a large number of identical delay cells, thus reducing overall device complexity while maintaining measurement precision.
2Manufacturing precision
If the delay step size is reduced for high-speed operation, then the delay accuracy is improved, but the number of delay cells required increases
Solution Approach 1:
The delay cell uses dynamic control signals to adjust the delay step size, enabling the same hardware to provide both coarse and fine delay adjustments. This eliminates the need to increase the number of delay cells to achieve high precision, as the single delay cell can adapt its step size dynamically based on operational requirements.
Solution Approach 2:
The delay cell is designed to perform multiple functions: it can operate in coarse adjustment mode for larger delay steps and fine adjustment mode for smaller delay steps. This multi-functionality allows a single delay cell to replace what would traditionally require multiple delay cells with different step sizes, reducing the total quantity of delay cells needed while maintaining high delay accuracy.
Data Source
AI summary
Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adjustable delay cell that delay transmission through the set delay cells of an input signal to the respective set delay cells an amount that does not vary responsive to the control signal. Delay cells that have an adjustable delay time are also provided.