Multi-Phase Clock Circuit With Shared Delay for Non-Overlap
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Solution Overview
Problem
Conventional circuits for generating multi-phase, non-overlapping clock signals in integrated circuits result in significant area overhead and introduce variations in delay time, leading to performance issues in digital signal processing circuits.
Innovation Solution
A circuit design that uses a single delay circuit to generate multiple non-overlapping clock signals, reducing area overhead and eliminating variations in delay time, while maintaining reliable and flexible generation of phase-shifted clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate delay circuits are used for each clock signal, then non-overlapping clock signals can be generated, but area overhead increases significantly
Solution Approach 1:
Multiple separate delay circuits are merged into a single shared delay circuit. The single delay circuit generates delayed versions of clock signals that are then distributed to multiple circuit modules through a combinatorial logic network, eliminating the need for separate delay circuits for each clock signal while maintaining the non-overlapping property.
Solution Approach 2:
The single delay circuit serves multiple functions by generating delayed clock signals for multiple different circuit modules. Instead of each module having its own dedicated delay circuit, the single delay circuit universally serves all modules, reducing overall area while maintaining functionality.
2Reliability
If separate delay circuits are used for each clock signal, then clock signals can be generated, but variations in delay time occur
Solution Approach 1:
Multiple separate delay circuits are merged into a single shared delay circuit. The single delay circuit generates delayed versions of clock signals that are then distributed to multiple circuit modules through a combinatorial logic network, eliminating the need for separate delay circuits for each clock signal while maintaining the non-overlapping property.
Solution Approach 2:
All clock signals pass through the same single delay circuit, ensuring they experience identical delay characteristics. This homogeneous treatment of all clock signals through a single path eliminates variations in delay time that would occur if different modules used different delay circuits with potential manufacturing tolerances.
3Reliability
If separate circuit arrangements are used for each clock signal, then non-overlapping clock signals can be generated, but device complexity increases
Solution Approach 1:
Multiple separate delay circuits are merged into a single shared delay circuit. The single delay circuit generates delayed versions of clock signals that are then distributed to multiple circuit modules through a combinatorial logic network, eliminating the need for separate delay circuits for each clock signal while maintaining the non-overlapping property.
Solution Approach 2:
The circuit is segmented into a single delay circuit portion and a combinatorial logic network portion. This segmentation allows the complex functionality to be divided into a simple delay element and a logic network that handles the distribution and non-overlapping enforcement, reducing overall device complexity compared to having complete separate arrangements for each clock signal.
Data Source
AI summary
A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.