Delay Line Cells With Logic-Gate Switching for Low-Power Signal Timing
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Solution Overview
Problem
Conventional delay line circuits face a trade-off between improving output signal characteristics and reducing power consumption, often requiring complex designs or resulting in undesirably high power consumption when attempting to enhance signal quality.
Innovation Solution
The proposed solution involves a series-connected delay line circuit with each delay cell comprising logic gates that manage signal transmission based on selection signals, utilizing NOR or NAND gates to control signal direction and minimize power consumption by maintaining duty cycle through even gate outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay line circuits use complex design to improve output signal characteristics, then the characteristics of output signal are improved, but power consumption increases undesirably high
Solution Approach 1:
The patent changes the logical parameters of the delay cells by using XOR gates instead of conventional buffer-multiplexer combinations. This parameter change in the logic structure allows the circuit to maintain improved output signal characteristics (duty cycle and timing margin) while reducing power consumption. The XOR gate configuration inherently minimizes level transitions, which directly reduces dynamic power consumption without sacrificing signal quality.
2Use of energy by moving object
If conventional delay line circuits reduce power consumption or circuit size, then power consumption is reduced, but the characteristics of output signal are degraded
Solution Approach 1:
The patent applies parameter changes by reconfiguring the delay cell logic using XOR gates, which fundamentally alters how the circuit operates. This new configuration achieves both low power consumption and high signal quality simultaneously, breaking the traditional trade-off. The XOR gate structure provides inherent duty cycle correction and timing margin improvement while maintaining low power operation through minimized signal transitions.
3Ease of operation
If delay cells use buffer and multiplexer configuration, then signal transmission is achieved, but circuit complexity increases and power consumption rises
Solution Approach 1:
The patent extracts and removes the multiplexer component from the delay cell configuration, replacing the entire buffer-multiplexer combination with a simpler XOR gate-based structure. This extraction of unnecessary components directly reduces circuit complexity while maintaining signal transmission functionality. The XOR gate configuration inherently provides the needed signal routing and delay functionality without requiring separate multiplexer control logic.
Data Source
AI summary
Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal. The third logic gate generates a third signal based on either a return signal or an output signal of the second logic gate.