Dual-Stage Delay Circuit for High-Resolution Microscope Timing
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Solution Overview
Problem
Existing delay circuits for microscopes are complex and have limited resolution for adjusting delay times, preventing arbitrary increases in clock rate and thus restricting the precision of signal delay in applications like confocal microscopy.
Innovation Solution
A circuit comprising a first delay unit and a second delay unit, where the second delay unit includes a converter and a shift register connected by n leads, allowing for high-resolution adjustable delays by shifting the boundary between input signals delayed by k and k-1 cycles of a clock signal, enabling flexible and precise control of signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional delay circuit with pulse shaper and shift registers is used, then the circuit can generate delayed control signals, but the circuit complexity increases and the resolution for adjusting delay times is limited
Solution Approach 1:
The delay circuit is segmented into two independent delay units: a first delay unit that delays the input signal by k cycles of a first clock signal, and a second delay unit that delays by additional cycles. This segmentation allows each unit to be optimized independently, reducing overall circuit complexity while achieving high-resolution delay adjustment through the combination of both units.
Solution Approach 2:
The invention introduces a second clock signal with a different frequency (n times the first clock frequency) to create a multi-dimensional delay control mechanism. By using two different clock domains (first clock for coarse delay, second clock for fine delay), the circuit achieves high resolution without increasing complexity in a single dimension, effectively adding a temporal dimension to the delay control.
2Measurement precision
If the clock rate of the shift register is increased to improve delay resolution, then the resolution increases within certain limits, but the circuit complexity prevents arbitrary increases in clock rate
Solution Approach 1:
The circuit employs dynamic clocking where the second shift register is clocked by a second clock signal whose frequency is n times that of the first clock signal. This dynamic approach allows the circuit to achieve high delay resolution without requiring the first shift register to operate at prohibitively high frequencies, thereby managing circuit complexity while improving precision.
Solution Approach 2:
A converter unit acts as an intermediary between the first delay unit and the second shift register. This converter translates the delayed signal from the first clock domain to the second clock domain, enabling the two delay units to work together seamlessly. The intermediary allows high-resolution delay without requiring the entire circuit to operate at the high frequency of the second clock.
3Adaptability or versatility
If a coarse delay and fine delay are generated using separate delay units, then the delay control range is improved, but the circuit construction becomes relatively complex
Solution Approach 1:
The invention merges the output of the first delay unit and the second delay unit through a converter and combines their delay effects. The first delay unit provides coarse delay (k cycles of first clock), while the second delay unit provides fine delay (additional cycles of second clock). By merging these two delay mechanisms, the circuit achieves wide delay control range without requiring an excessively complex single-unit design.
Data Source
AI summary
A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value xt<sub2>—</sub2>k and transfer the input signal to the second delay unit. The second delay unit includes a converter and a second shift register. The converter is connected to the second shift register by n leads. The value xt<sub2>—</sub2>k and a value xt<sub2>—</sub2>k−1 are present at the converter, where xt<sub2>—</sub2>k−1 is the input signal delayed by k−1 cycles of the first clock signal, The converter is configured such that the value xt<sub2>—</sub2>k−1 is present on leads 1 to m and the value xt<sub2>—</sub2>k is present on leads m+1 to n. The second shift register is configured to successively output values present on leads 1 to n.