Memory Delay Circuit Using Clock-Referenced Integer Multiples
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Solution Overview
Problem
Existing semiconductor memory devices face instability in generating a delayed signal with a consistent delay time, as the elongated delay time is not effectively prevented from occurring.
Innovation Solution
A semiconductor memory device is designed with a reference signal generator that produces a reference signal representing the clock period, which is used by a delay circuit to delay input signals by a time obtainable by multiplying the reference delay time by a positive integer, ensuring a more stabilized delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay circuit is used to delay input signals, then the delay time can be adjusted, but the delay time becomes unstable and may be elongated
Solution Approach 1:
The patent changes the parameter basis for delay time from direct voltage control to multiplication of a stabilized reference delay time by an integer coefficient. This transforms the delay time calculation from Td = f(Vcc) to Td = N × Tref, where Tref is derived from the clock period. This parameter transformation stabilizes the delay time against voltage fluctuations while maintaining adjustability through the integer coefficient N.
Solution Approach 2:
The patent introduces a feedback mechanism where the clock signal, which has a stable and accurate period, is used to generate the reference delay time. The delay circuit's operation is referenced back to this stable clock signal, ensuring that any variations in power supply voltage do not directly affect the delay time. The relationship Td = N × Tref creates a feedback-based stabilization where the stable clock period anchors the delay time accuracy.
2Adaptability or versatility
If voltage change is used to adjust delay time, then delay time can be shortened or elongated, but elongated delay time cannot be prevented
Solution Approach 1:
The patent transforms the delay time control mechanism from direct voltage proportionality to integer multiplication of a reference value. Instead of Td being directly proportional to Vcc, the new approach uses Td = N × Tref where N is an integer coefficient. This parameter change allows flexible adjustment through different integer values while the reference delay time Tref remains stable and is not directly affected by voltage fluctuations, thus preventing unwanted elongation.
Solution Approach 2:
The patent introduces dynamic selectability of delay time through multiple integer coefficients (N1, N2, N3, ...) that can be chosen based on different operating conditions. The system can dynamically switch between different delay times by selecting different integer coefficients, while each selected delay time is guaranteed to be stable because it is derived from the stable reference delay time multiplied by an integer, rather than being directly controlled by variable voltage.
Data Source
AI summary
Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.