Bias-Controlled Duty Correction Circuit for Precise Clock Timing
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Solution Overview
Problem
Existing duty ratio correction circuits in digital circuits face challenges in precisely adjusting duty ratios due to variations in transistor characteristics caused by manufacturing process dispersions, making it difficult to achieve high-speed adjustments in short clock periods.
Innovation Solution
A duty correction circuit comprising multiple stages of delay circuits with inverters and bias circuits that adjust the input clock signal by varying bias voltages, allowing for precise control of delay times and duty ratios, regardless of transistor characteristic variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional duty correction circuits use PMOS and NMOS transistors to adjust duty ratios, then duty ratio adjustment is possible, but manufacturing process dispersions cause transistor characteristic variations that prevent precise duty ratio control
Solution Approach 1:
The patent changes the control parameter from transistor characteristics (which vary due to manufacturing dispersions) to bias voltages applied to delay circuits. By controlling the delay time through bias voltage rather than relying on fixed transistor characteristics, the circuit achieves precise duty ratio control independent of manufacturing variations.
Solution Approach 2:
The patent introduces delay circuits as intermediary elements between the clock signal and the output. These delay circuits allow independent adjustment of signal timing through bias control, separating the duty ratio control function from the transistor characteristics and enabling precise adjustment despite manufacturing variations.
2Speed
If duty correction circuits are designed for high-speed operation in short clock periods, then processing speed increases, but adjustment precision decreases due to limited time for waveform adjustment
Solution Approach 1:
The patent makes the delay circuits dynamically adjustable through bias voltage control. The delay time can be continuously adjusted by changing the bias voltage, allowing the circuit to adapt to different clock periods and achieve precise duty ratio correction even in high-speed short clock period operations.
Solution Approach 2:
The patent applies delay correction in advance to the clock signal before it is used in digital circuits. By pre-adjusting the duty ratio through controlled delay circuits, the circuit ensures accurate timing is established before signal processing begins, enabling high-speed operation with maintained precision.
3Reliability
If multiple transistors are adjusted to compensate for manufacturing variations, then characteristic matching improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the duty ratio control function from the transistor characteristics themselves and places it in separate delay circuits with bias control. This separation removes the dependency on precise transistor matching, simplifying the overall circuit design while maintaining reliable duty ratio correction.
Data Source
AI summary
A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.