Asynchronous Delay Insertion Circuit for Timing Attack Resistance
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Solution Overview
Problem
Existing asynchronous circuits are vulnerable to delay-based attacks, such as power analysis and electromagnetic radiation analysis, which can compromise the integrity and confidentiality of information by revealing the operations performed on signals.
Innovation Solution
The implementation of a delay insertion circuit with a Muller gate and multiple delay circuits connected in series, where each delay circuit's output is connected to a multiplexing circuit, allowing for dynamic programmable delays between a minimum and maximum value, and a feedback mechanism to ensure that transitions are propagated with a time interval greater than or equal to the maximum delay, making the circuit insensitive to timing attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed predetermined number of delay circuits are used, then the circuit structure is simple, but the delay value cannot be changed dynamically and energy consumption patterns become predictable
Solution Approach 1:
The patent implements dynamic delay adjustment by replacing the fixed predetermined number of delay circuits with a variable counter that can be programmed to different values. The counter is loaded with a programmable number N and decremented with each clock cycle, allowing the delay duration to be dynamically changed without modifying the hardware structure. This resolves the contradiction by enabling adaptability while maintaining structural simplicity.
Solution Approach 2:
The patent changes the parameter of delay circuit count from a fixed hardware value to a programmable software-controlled value. By loading different values into the counter register, the system can dynamically adjust the number of active delay circuits, thereby changing the total delay value without physical reconfiguration. This parameter change approach allows flexible adaptation while keeping the circuit structure unchanged.
2Ease of manufacture
If the same basic delay circuit is activated multiple times, then the circuit design is simplified, but the delay value becomes dependent on the predetermined number and cannot be changed dynamically
Solution Approach 1:
The patent introduces a dynamic control mechanism using a programmable counter that determines how many times the basic delay circuit is activated. Instead of hardcoding the activation count in the circuit design, the counter can be loaded with different values at runtime, enabling dynamic adjustment of the total delay while reusing the same basic delay circuit module. This maintains ease of manufacture through module reuse while adding adaptability through software control.
3Use of energy by moving object
If energy consumption is used for delay insertion, then the delay can be controlled, but the energy consumption pattern reveals information about the delay value to attackers
Solution Approach 1:
The patent implements a feedback mechanism where the counter value is decremented with each clock cycle and compared against zero to determine when to stop activating delay circuits. This feedback-controlled approach ensures that the delay duration precisely matches the programmed value N, providing accurate delay control. The regular clock-cycle-based decrement pattern creates a predictable energy consumption profile that is less susceptible to timing attacks compared to irregular delay mechanisms.
Solution Approach 2:
The patent uses periodic clock cycles to control the activation of delay circuits. The counter is decremented at regular clock intervals, creating a periodic activation pattern that is synchronized with the system clock. This periodic action makes the energy consumption pattern regular and predictable, reducing the information leakage that could be exploited by timing attacks while maintaining precise delay control through the programmed counter value.
Data Source
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AI summary
The circuit has a delay insertion circuit comprising a Muller gate (5) and a set of delay circuits (D1-Dn) connected in series to an output (S0) of the Muller gate between a signal input (S) and a signal output (Sd). Each delay circuit has an output connected to corresponding inputs (M1-Mn) of a multiplexing circuit whose output constitutes an output of the delay insertion circuit. The Muller gate has an input constituting an input of the delay insertion circuit and another input connected to an output (Sn) of the last delay circuit (Dn) through an inverter gate (6).