CMOS Time-Delay Buffer Using Partial Silicide Gate Resistance
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Solution Overview
Problem
Conventional time delay devices formed below the 100 nm process are space-intensive and adjusting their dimensions affects sub-threshold characteristics, making them inefficient for synchronizing logic signals.
Innovation Solution
A time-delay circuit with a CMOS inverter having a PMOS and NMOS transistor, where a silicide layer is partially disposed on the transistor gate, increasing parasite resistance and allowing a single time-delay buffer to determine delay time, and additional non-silicide regions can be used to adjust delay time without occupying excessive space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple inverters are connected in series to achieve time delay, then the delay time can be adjusted, but the device occupies excessive space
Solution Approach 1:
The patent changes the physical parameters of the transistor gate by selectively forming silicide layers on only some of the gates in the inverter chain. This parameter change (presence or absence of silicide) allows adjustment of delay time while using fewer inverters, thereby reducing the device area occupied
Solution Approach 2:
The patent applies different local qualities to different gates within the inverter chain. Specifically, some gates have silicide layers formed on them while others do not, creating local variations in resistance that control the delay time without requiring all inverters to be present or fully functional
2Loss of time
If the width or length of inverter channel is adjusted to change delay time, then the delay time can be controlled, but the sub-threshold characteristics are affected
Solution Approach 1:
Instead of changing the channel width or length, the patent changes the resistance parameter by selectively forming silicide layers on transistor gates. This alternative parameter change achieves delay time control without affecting the sub-threshold characteristics that would be compromised by dimensional changes
Solution Approach 2:
The patent substitutes the mechanical/geometric approach (changing channel dimensions) with an electrical approach (changing resistance through silicide formation). This substitution allows delay control while preserving the physical integrity and electrical characteristics of the transistor channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides efficient signal synchronization with reduced space usage, allowing for more devices on a chip and adjustable delay times, while maintaining high-quality logic signals and equal rise/fall times.
Implementation Method 1
the silicide layer is partially disposed on portion of the transistor gate that may increases the parasite resistance of the CMOS inverter
Data Source
AI summary
A time-delay buffer having a CMOS inverter and a capacitor is disclosed. The CMOS inverter of the time-delay buffer has a silicide layer partially disposed on the transistor gate of the CMOS and a non-silicide region lain in between the silicide layers. Therefore, the time-delay buffer of the present invention has a resistance therein, and results in a period of time delayed in the circuit.