Phase Interpolator Bias Control for Uniform Multi-Phase Clocks

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Solution Overview

Problem

Existing multi-phase interpolation devices face challenges in generating uniform multi-phase clock signals due to variations in process and temperature, which affect the uniformity of output clock signals.

Innovation Solution

A phase interpolator design incorporating a differential to single-ended converter, load circuit, differential pairs, current source, and switch pair, where the switch pair controls the bias state of the differential pairs and regulates the load circuit and reference current to ensure the intersection of signals occurs within the overlap duration between input clocks, maintaining uniformity across output clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional multi-phase interpolation devices are used to generate multi-phase clock signals, then the output clock signals can be generated, but the uniformity of output clock signals deteriorates due to process and temperature variations

Engineering Contradiction:

Improveuniformity of output clock signalsVSAvoidprocess and temperature variations

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent replaces conventional interpolation methods with a differential pair-based circuit system that uses electrical signal processing instead of mechanical or conventional electronic approaches. The differential pairs convert input clock signals into differential signals that are less susceptible to process and temperature variations, thereby improving output uniformity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters of the circuit by using differential signaling and adjusting bias currents through current sources. This allows the circuit to maintain consistent performance across varying process and temperature conditions by dynamically adapting the electrical parameters of the differential pairs.

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If the intersection of first signal and second signal is not controlled to be in the overlap duration, then circuit operation is simpler, but the uniformity of multi-phase output clock signals deteriorates

Engineering Contradiction:

Improveuniformity of multi-phase output clock signalsVSAvoidcontrol of signal intersection timing

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-positioning the intersection of the first and second signals within the overlap duration of the input clocks through bias control. This is achieved by configuring the differential pairs and current sources to naturally produce signal intersections that fall within the desired time window, eliminating the need for complex real-time adjustment mechanisms.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent employs feedback mechanisms where the output of the differential pairs is fed back to adjust the bias conditions, ensuring that the signal intersection remains within the overlap duration. This feedback control stabilizes the timing of the intersecting signals and maintains uniformity in the generated multi-phase clock outputs.

Inventive Principle:

Principle #23Feedback

3Manufacturing precision

If differential pairs are used to improve signal uniformity, then output clock uniformity is improved, but the device complexity increases due to additional components

Engineering Contradiction:

Improveuniformity of output clock signalsVSAvoidnumber of circuit components

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the differential pair structure, which simultaneously performs signal differential conversion, noise rejection, and timing control. By combining these functions into a single circuit topology, the patent reduces the need for separate components while maintaining improved signal uniformity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The differential pairs in the patent serve multiple purposes: they convert single-ended clock signals to differential signals, provide immunity to common-mode noise, control signal intersection timing, and generate uniform multi-phase outputs. This multi-functionality reduces overall device complexity despite the use of differential pair structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8664993B2Phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method

Publication Date: 2014.03.04 REALTEK SEMICON CORP

AI summary

A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated.