Duty Cycle Correction Using Phase Mixer and Feedback Loop
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Solution Overview
Problem
Conventional duty cycle correction devices for clock signals in semiconductor memory chips have a poor correcting ability for achieving a 50% duty cycle, which is essential for synchronous memory devices like DDR and DDR2.
Innovation Solution
A duty cycle correction device that uses a phase mixer to combine two clock signals from a delay locked loop (DLL) circuit, with a phase splitter, duty detection unit, combination unit, and shift register to adjust the mixing ratio, ensuring the output clock signals have a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay circuit is used to adjust the duty cycle of the internal clock, then the duty cycle can be adjusted, but the correcting ability for the duty cycle is very poor
Solution Approach 1:
The patent employs a delay locked loop (DLL) device that dynamically adjusts the phase and duty cycle of the internal clock signal in real-time to match the external clock signal. The DLL continuously monitors the phase difference and automatically corrects the duty cycle through feedback control, making the correction process dynamic rather than static. This resolves the contradiction by providing both adjustability and high correcting ability through continuous dynamic optimization.
Solution Approach 2:
The duty cycle correction device incorporates a feedback mechanism where the duty cycle detection unit monitors the internal clock signal and feeds this information back to the DLL device. The DLL uses this feedback to automatically adjust the delay elements and inverters, thereby correcting the duty cycle. This closed-loop feedback system ensures high correcting ability and precision, directly addressing the limitation of conventional delay circuits.
2Reliability
If the duty cycle of the internal clock is not set to 50%, then the synchronization with external clock edges cannot be achieved, but adjusting the duty cycle with conventional methods results in poor correction precision
Solution Approach 1:
The DLL device dynamically adjusts the duty cycle through controlled delay elements that respond to phase difference detection. By continuously optimizing the delay through feedback, the system achieves precise 50% duty cycle adjustment, enabling reliable synchronization with external clock edges while maintaining high correction precision.
Solution Approach 2:
The patent changes the delay parameter of the delay elements and the switching state of inverters within the DLL to adjust the duty cycle. By varying these parameters dynamically based on feedback from the duty cycle detection unit, the system achieves precise duty cycle control, ensuring both synchronization capability and adjustment precision.
3Device complexity
If a simple delay circuit is used for duty cycle correction, then the device complexity is low, but the correcting ability and precision are poor
Solution Approach 1:
The DLL device serves multiple functions: phase alignment, duty cycle correction, and frequency matching. By integrating these functions into a single universal device rather than using separate simple delay circuits, the patent achieves high correction precision while managing complexity through functional integration. The DLL's multi-functionality resolves the contradiction by providing precise correction without requiring multiple separate components.
Solution Approach 2:
The feedback mechanism in the DLL allows the system to automatically optimize its performance without requiring complex manual adjustment circuits. The feedback loop continuously monitors and adjusts the duty cycle, providing high precision correction while keeping the overall device structure relatively simple through automated control rather than complex hardware.
Data Source
AI summary
Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.