Internal Clock Generation Using 180° Phase Recombination
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Solution Overview
Problem
High-frequency external clock signals in synchronous integrated circuits introduce significant phase shifts and duty cycle distortions due to internal circuitry delays, which can lead to invalid commands and data integrity issues, especially in low power and low pin count applications.
Innovation Solution
A clock generator system using two clock buffers with a 180-degree phase difference to produce an internal clock signal, ensuring consistent delays and minimizing duty cycle distortions through the combination of pulses from one-shot pulse generators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the external clock signal is increased to increase the data transfer rate, then the productivity is improved, but the phase shift between internal and external clock signals becomes more significant due to internal circuitry delays
Solution Approach 1:
The patent divides the clock signal path into two separate buffered paths (first clock buffer and second clock buffer) that are substantially identical. By segmenting the clock distribution and using identical buffering paths for both external clock inputs, the system ensures that delays are matched and phase relationships are preserved even at high frequencies
Solution Approach 2:
The patent introduces a 180-degree phase shift between the first and second external clock signals. This asymmetric phase relationship is deliberately used to create complementary clock signals that, when processed through identical buffers, maintain precise phase relationships for latching operations
2Productivity
If the frequency of the external clock signal is increased, then the productivity is improved, but the duty cycle variations introduce greater duty cycle error
Solution Approach 1:
The patent uses the output of the first clock buffer (which has consistent delays) as a feedback signal to control the one-shot pulse generator. This feedback mechanism ensures that the internal clock signal's duty cycle is regulated based on the actual delayed clock signal, compensating for variations introduced at high frequencies
Solution Approach 2:
The patent changes the operational parameters of the one-shot pulse generator based on the delayed clock signal characteristics. By adjusting the pulse generation timing according to the actual clock signal parameters (which include the consistent delays from buffering), the system maintains accurate duty cycles even when external clock frequency and duty cycle vary
3Device complexity
If a single clock buffer is used to generate the internal clock signal, then the device complexity is reduced, but duty cycle distortions occur at high frequencies and low voltages
Solution Approach 1:
The patent introduces a one-shot pulse generator as an intermediary component between the buffered clock signals and the internal clock output. This intermediary device uses the consistently delayed clock signals from the buffers to generate precise timing pulses, acting as a mediator that translates the buffered clock edges into accurate internal clock transitions without introducing additional distortions
Data Source
AI summary
A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.