Timing Generator Circuit With Delay-Canceling Comparator Reference
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Solution Overview
Problem
Existing timing generators in semiconductor devices suffer from parasitic delays and variations due to temperature and semiconductor process dependencies, leading to inaccurate time intervals.
Innovation Solution
A timing generator design that utilizes a reference generator and comparator with threshold voltage variations that cancel each other, employing MOS transistors with gate-to-source threshold voltages to set and compare reference voltages, and bias transistors to track these voltages, reducing temperature and process variation impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a comparator with internal delay is used to generate timing intervals, then the timing generator can be implemented with standard semiconductor components, but the output signal changes state at a delayed time rather than when the capacitor voltage reaches the reference value
Solution Approach 1:
The patent introduces an intermediary latch circuit between the capacitor-voltage comparison process and the output signal. The latch is triggered by the comparator output but changes state based on the capacitor voltage at a specific moment (when it reaches halfway to Vref), not when the comparator output changes. This intermediary mechanism decouples the timing reference from the comparator's internal delay, allowing standard components to be used while achieving accurate timing measurement.
2Ease of manufacture
If a standard comparator is used in the timing generator, then the device can be manufactured with conventional processes, but the delay time varies with temperature and semiconductor process variations
Solution Approach 1:
The patent employs feedback through the latch circuit that continuously monitors the capacitor voltage and uses it to control the output state. The latch is set when the capacitor voltage reaches halfway to Vref and resets when the capacitor discharges to zero. This feedback mechanism creates a timing reference that is based on the capacitor's voltage trajectory rather than the comparator's delayed response, making the timing interval independent of temperature and process variations affecting the comparator.
3Device complexity
If the comparator output is used directly as the timing signal, then the circuit complexity is minimized, but the time period generated is inaccurate due to parasitic delay
Solution Approach 1:
The patent performs preliminary action by having the latch circuit prepare to change state based on the capacitor voltage reaching a predetermined threshold (halfway to Vref) before the comparator output actually changes. The latch is designed to trigger at this intermediate voltage point, anticipating the comparator's delayed response. This preliminary timing reference allows the circuit to maintain simplicity while achieving accurate time period measurement by referencing an earlier event in the charging cycle.
Data Source
AI summary
In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.