Non-Overlapping Clock Generator With Feedback-Stable High-Frequency Startup

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Solution Overview

Problem

Current non-overlapping clock generation schemes for passive mixers in RF communication devices face limitations such as low frequency operation, uncertain startup behavior, and flicker noise coupling, particularly in high-frequency applications.

Innovation Solution

A high-frequency non-overlapping clock generator design utilizing consecutively coupled register cells with feedback nodes and direct input-to-output coupling, which ensures stable operation by maintaining only one register cell at a HIGH state at any given time, reducing uncorrelated noise and improving startup stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional non-overlapping clock generation schemes are used, then the circuit can operate, but the frequency of operation is limited to low frequencies

Engineering Contradiction:
Improvefrequency of operationVSAvoidstartup behavior stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The clock generation function is segmented into multiple independent register cells (first, second, third, and fourth register cells) that operate in a cyclic sequence. Each register cell generates one phase of the non-overlapping clock signals, allowing the system to achieve high-frequency operation while maintaining stable startup behavior through the distributed architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Feedback connections are implemented between register cells to ensure proper sequencing and stable operation. The output of each register cell feeds back to control the next register cell in the sequence, creating a self-sustaining cyclic operation that guarantees reliable startup and continuous high-frequency operation.

Inventive Principle:
Principle #23Feedback

2Object-affected harmful factors

If conventional clock generation schemes are used, then the circuit can function, but uncorrelated noise (flicker noise) couples into the output

Engineering Contradiction:
Improveuncorrelated noiseVSAvoidcircuit structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The clock generation is divided into separate register cells, each handling a specific phase. This segmentation isolates noise sources within individual cells and prevents flicker noise from coupling across the entire system, as each cell operates independently with its own stable state mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each register cell is designed with specific local properties (non-overlapping output stages, feedback connections) that ensure low noise performance. The local quality of each cell contributes to the overall low noise figure of the system, with each cell generating clean clock phases without introducing uncorrelated noise.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If conventional clock generation schemes are used, then the circuit can operate, but mode selection becomes difficult

Engineering Contradiction:
Improvemode selection capabilityVSAvoidoperation simplicity
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The register cell architecture is designed to be universal and adaptable to different operating modes. The same basic register cell structure can generate different numbers of non-overlapping phases (e.g., 2-phase, 4-phase, or more) by configuring the feedback connections and input signals, providing mode selection capability without requiring different circuit topologies.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8618859B1Generating high-frequency, non-overlapping clocks
Publication Date: 2013.12.31 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8618859B1 patent drawing
  • US8618859B1 patent drawing
  • US8618859B1 patent drawing

AI summary

A method for generation of high frequency, non-overlapping clocks may include receiving input clock signals at a clock input node of a circuit. Multiple feedback signals may be received at a number of input feedback nodes of the circuit. At a startup node, a startup signal of the circuit may be received, and, in response to receiving the startup signal, an output clock may be generated at a predefined portion of at least one of the received input clock signals. A stable high frequency output clock may be generated at an output stage by utilizing the feedback signals received by the input feedback nodes.