Clock Delay Adjustment Circuit for Multi-Macro Fault Recovery
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Solution Overview
Problem
The existing semiconductor IC manufacturing processes face challenges in managing delay faults across multiple macros within a chip, leading to increased circuit size requirements for nonvolatile memory circuits to store recovery information, which complicates the recovery of delay malfunctions.
Innovation Solution
A clock signal adjustment circuit with a reduced number of delay setting circuits that store and dispatch delay control signals based on the results of a delay test, allowing for efficient recovery of delay malfunctions without expanding the circuit size, utilizing a recovery group memory circuit and a delay setting dispatch control circuit to manage the recovery process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay setting circuits are provided for each macro to store recovery information, then delay fault recovery capability is improved, but circuit size increases
Solution Approach 1:
A small number of delay setting circuits are designed to serve multiple macros through time-multiplexed operation. The control circuit dynamically assigns these shared circuits to different macros based on test results, allowing one circuit to store recovery information for multiple macros sequentially rather than requiring dedicated circuits for each macro.
Solution Approach 2:
The system transitions from a static one-to-one mapping between delay setting circuits and macros to a dynamic many-to-one relationship. The control circuit enables temporal sharing of delay setting circuits by switching their assignment based on which macro requires recovery, optimizing resource utilization while maintaining full recovery capability across all macros.
2Area of stationary object
If the number of delay setting circuits is reduced, then circuit size is minimized, but the ability to manage delay faults across multiple macros deteriorates
Solution Approach 1:
A control circuit acts as an intermediary between the reduced number of delay setting circuits and the multiple macros. This control circuit manages the assignment and switching of delay setting circuits to different macros, ensuring that each macro can still receive appropriate recovery information through the shared circuits without requiring dedicated circuits for each macro.
Solution Approach 2:
The system performs delay testing and identifies macros requiring recovery before finalizing the assignment of delay setting circuits. This preliminary identification allows the control circuit to optimally assign the limited delay setting circuits to the specific macros that need recovery, ensuring full recovery capability is maintained with minimal circuit resources.
Data Source
AI summary
A clock signal adjustment circuit in a semiconductor integrated circuit includes: multiple circuit blocks; multiple clock delay circuits supplying delayed clock signals of the input clock signals under the control of the delay control signals to the corresponding circuit blocks; a control circuit conducting a delay test of the circuit blocks; a recovery group memory circuit storing information in the circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; delay setting circuits storing information about the delay value for circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; and a delay setting dispatch control circuit dispatching the delay control signal corresponding to the delay value information stored in the delay setting circuit to the clock delay circuits corresponding to the information about the circuit blocks stored in the recovery group memory circuit.