Clock Conditioning Circuit for Low-Jitter Phase-Shifted Sampling
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Solution Overview
Problem
Existing signal processing systems using CDMA or WCDMA methods face challenges in reducing jitter in sampling signals, which introduces noise and reduces the accuracy of digital output signals, particularly when down converting reference frequencies to lower sampling frequencies without increasing power consumption.
Innovation Solution
A clock conditioning circuit that provides down converted and phase-shifted clock signals with reduced jitter, adjusting frequency and phase differences without increasing the reference frequency, using encoded clock signals to control the characteristics of the clock signals, such as period, duty cycle, and symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reference frequency is increased to reduce jitter, then jitter in sampling signal is reduced, but power consumption increases
Solution Approach 1:
The patent changes the frequency parameter by using a high reference frequency (e.g., 1.5 GHz or 2 GHz) and then applying integer division to down-convert it to the desired sampling frequency. This allows the system to benefit from the lower jitter of higher frequencies while consuming less power than would be required to directly operate at those high frequencies for sampling.
2Adaptability or versatility
If reference frequency is divided by two different integer values to generate sub-frequencies and averaged, then sampling frequency is obtained, but jitter is introduced in the sampling signal
Solution Approach 1:
The patent segments the frequency division operation into multiple parallel integer dividers that operate independently on the same reference clock signal. Each divider produces a down-converted clock signal with a specific phase relationship, and these are combined through logical operations to produce the final sampling clock. This segmentation approach maintains signal integrity while achieving frequency flexibility.
Solution Approach 2:
The patent uses periodic logical operations (AND, OR gates) combined with phase shifters to select and combine clock signals from different dividers. By using periodic selection based on the reference clock phases, the system generates sampling clocks with controlled phase relationships without introducing jitter, unlike simple averaging methods.
3Adaptability or versatility
If phase difference between sampling signals changes randomly due to skew, then time points for sampling are affected, but jitter is introduced and accuracy is reduced
Solution Approach 1:
The patent implements feedback through phase detector circuits that monitor the phase relationships between clock signals from different dividers. The phase detectors generate control signals that adjust the timing of clock distribution to maintain precise phase relationships, compensating for any skew that occurs during signal transmission and ensuring accurate sampling timing.
Data Source
AI summary
A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.