Memory Input Latch Timing Using Delayed Clock Selection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing data signals with clock signals due to variations in voltage, temperature, and wire delay, leading to erroneous signal determination and write operations, especially at high clock frequencies, where setup/hold time is difficult to maintain.
Innovation Solution
A semiconductor memory device with an input signal delaying circuit, delayed clock generation circuit, and input signal latch timing determination circuit that automatically selects a delayed clock to synchronize data signals with the clock, eliminating the need for complex clock tests and sequencer circuits, and allowing for arbitrary setting of latch timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve productivity, then the data processing speed is improved, but the setup/hold time becomes difficult to maintain leading to erroneous signal determination
Solution Approach 1:
The patent applies preliminary action by delaying the clock signal in advance using a delay circuit before it reaches the latch circuit. This preliminary delay adjustment ensures that the clock edge arrives at the optimal time to satisfy setup and hold time requirements, preventing erroneous signal determination even at high clock frequencies. The delay amount is determined through a test operation that identifies the optimal timing configuration.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the delay parameter of the clock signal. The delay circuit modifies the timing parameter of the clock signal based on test results, allowing the system to adapt to varying clock frequencies and maintain reliable signal determination. This parameter adjustment resolves the contradiction between high-speed operation and accurate signal latching.
2Measurement precision
If a dedicated test operation is performed to determine optimal latch timing, then the signal synchronization accuracy is improved, but the device complexity and operation time increase
Solution Approach 1:
The patent applies self-service by implementing a test operation that automatically determines the optimal delay amount without requiring external intervention or complex test equipment. The semiconductor memory device performs the test operation internally, using its own resources to identify the optimal latch timing configuration. This self-determination process simplifies the overall system complexity while maintaining high timing accuracy.
Solution Approach 2:
The patent employs feedback mechanisms where the test operation results are used to adjust and optimize the delay circuit parameters. The system performs a test operation, measures the actual timing performance, and uses this feedback information to determine the optimal delay amount. This closed-loop approach ensures accurate latch timing determination while keeping the device complexity manageable through systematic optimization.
3Reliability
If the setup/hold time is increased to ensure reliable signal latching, then the signal determination reliability is improved, but the clock frequency must be reduced
Solution Approach 1:
The patent applies dimensionality change by introducing a time delay dimension to the clock signal path. Instead of simply increasing setup/hold time, the system adds a controllable delay dimension that allows precise timing adjustment. This additional temporal dimension enables the system to maintain reliable signal latching while operating at higher clock frequencies, effectively decoupling the trade-off between reliability and productivity.
Solution Approach 2:
The patent employs dynamics by making the clock delay amount adjustable and optimizable rather than fixed. The delay circuit can be dynamically configured based on operating conditions, allowing the system to adapt to different clock frequencies and signal timing requirements. This dynamic adjustment capability enables the system to maintain optimal timing margins across a wide range of operating conditions, simultaneously achieving high reliability and high productivity.
Data Source
AI summary
A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to thereby generate a plurality of delayed clocks; a plurality of delayed input signal holding circuits for holding the delayed input signal on the plurality of delayed clocks, respectively; an input signal latch timing determination circuit for outputting a determination signal indicating a timing at which to latch the delayed input signal, based on a plurality of held signals held by the delayed input signal holding circuits; and a held signal selector circuit for integrating the plurality of held signals into a single signal.