Linear Phase Interpolation Circuit Using Unary Code Encoding

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Solution Overview

Problem

Existing phase interpolation circuits exhibit non-linear control relationships between phase control signals and output phase offsets, leading to inconsistent phase changes as the control value approaches its extremes, which affects the accuracy and reliability of phase interpolation in digital communications systems.

Innovation Solution

The implementation of a phase interpolator using polar vector rotation and encoding control signals in unary code to minimize vector amplitude and phase errors, with NMOS gates sourcing fixed currents and selectively connecting gate outputs to a common summation node to achieve linear phase relationships, reducing power consumption and improving linearity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional phase interpolation circuits are used, then phase offset generation is achieved, but non-linear control relationship causes inconsistent phase changes

Engineering Contradiction:
Improvephase interpolation accuracyVSAvoidconsistency of phase changes
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent transforms the control signal from binary to unary code representation, fundamentally changing the parameter encoding method. This allows each bit position in the unary code to directly control a specific current weight, creating a linear relationship between control signal and output phase where equal increments in control value produce equal phase changes, resolving the non-linearity issue of conventional circuits

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent divides the phase control into multiple discrete current sources, each corresponding to a specific bit position in the unary control code. Each current source contributes a fixed weighted current to the summation node, segmenting the overall phase control into independent, linearly-scalable components that collectively achieve precise and consistent phase interpolation

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If more control bits are added for higher resolution, then phase resolution improves, but power consumption increases

Engineering Contradiction:
Improvephase resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The unary code implementation activates only the number of current sources equal to the desired resolution level, rather than maintaining all possible current sources active. For example, to achieve 4-bit resolution, only 4 out of potentially 16 current sources are activated, reducing power consumption to match the actual resolution requirement while maintaining the ability to provide higher resolution if needed

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the control signal representation to unary code, where the magnitude of the control value directly corresponds to the number of active current sources. This parameter transformation allows the control signal itself to encode both the resolution level and the phase position, eliminating the need for additional control logic and reducing overall power consumption while maintaining high resolution

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10488227B2Linear phase interpolation circuit
Publication Date: 2019.11.26 KANDOU LABS SA
  • US10488227B2 patent drawing
  • US10488227B2 patent drawing
  • US10488227B2 patent drawing

AI summary

Methods and systems are described for receiving a control step input at a binary-to-thermometer decoder and responsively generating bits of a thermometer codeword representative of the control step input, providing the bits of the thermometer codeword to a plurality of differential pairs comprising a first transistor and a second transistor, each differential pair configurable for one of directing current to an in-phase (I) common node or directing current to a quadrature phase (Q) common node and switching between directing current to the I common node and the Q common node, and forming an output signal based on current drawn through the I and Q common nodes, the output signal having an intermediate phase with respect to a first and a second reference signal.