Clock Tree Delay Segments for Fine-Grained Balancing
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Solution Overview
Problem
Existing clock balancing technologies require a large number of delay units with low delay resolution, leading to increased costs and layout inefficiencies, as they aim to maintain latency or delay time balance between clock trees and sub-trees.
Innovation Solution
A clock circuit with a delay module comprising multiple delay segments, each with a consistent delay time caused by a connection net, allowing for efficient delay time allocation and reduced number of delays, suitable for both inter-clock and intra-clock balancing technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay units (buffers) are added one by one into the clock tree to balance delay time, then the clock tree can be balanced, but the number of delay units increases leading to higher cost and larger layout area
Solution Approach 1:
The patent combines the delay function with the connection net structure, merging two separate elements (delay unit and connection net) into a unified approach. Instead of adding discrete delay units to balance clock trees, the invention uses the inherent delay capability of connection nets with different lengths to achieve the same balancing objective, thereby reducing the number of additional components needed.
Solution Approach 2:
The connection net is given a dual function: it serves both as a signal transmission path and as a delay element for clock balancing. By making the connection net multi-functional, the patent eliminates the need for separate delay units in many cases, reducing overall device complexity while maintaining clock tree balancing capability.
2Loss of time
If delay units (buffers) are used for delay, then delay time can be achieved, but the minimum delay time of each buffer results in low delay resolution
Solution Approach 1:
The patent changes the parameter of delay implementation from discrete buffer-based delay to continuous connection net length-based delay. By varying the length of connection nets, the invention achieves fine-grained delay adjustment with high resolution, overcoming the fixed minimum delay step imposed by buffer-based approaches.
3Adaptability or versatility
If a larger number of delay units are used for clock balancing, then delay time can be adjusted, but cost and layout area increase
Solution Approach 1:
The patent merges the delay function into the connection net structure, eliminating the need for separate delay units. This integration reduces the total layout area while preserving the ability to adjust delay time through connection net length variation, thus maintaining adaptability without increasing area.
Data Source
AI summary
A clock circuit with delay functions includes a first clock tree and a delay module. The first clock tree provides a first clock signal and includes a first clock root and a plurality of first sub-trees. The delay module is coupled to the first clock root or a designated sub-tree among the plurality of first sub-trees for delaying the first clock signal. The delay module includes at least two delay segments, wherein each delay segment includes a delay and a connection net. The delay time caused by each delay segment is substantially the same.