Clock Signal Delay Layout for Lower Output Waveform Distortion
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Solution Overview
Problem
Conventional methods for improving output waveform distortion of clock signals, such as using individual power supplies or regulators for each output, are either impractical due to pin limitations or increase circuit area and cost.
Innovation Solution
A semiconductor device with a delay unit that generates multiple clock signals of the same frequency by providing a predetermined delay time period to the input clock signal, reducing the load on the power supply and minimizing waveform distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple clock signals are output simultaneously with the same frequency, then the electronic apparatus can operate efficiently, but the load on the power supply increases causing output waveform distortion
Solution Approach 1:
The patent applies preliminary action by delaying clock signals before they are output simultaneously. The delay unit introduces predetermined delay time periods to spread out the simultaneous switching events, preventing power supply load spikes that cause waveform distortion while still delivering multiple clock signals to maintain operational efficiency
2Object-affected harmful factors
If individual power supplies are provided for each clock signal output, then output waveform distortion is reduced, but the device complexity and pin requirements increase
Solution Approach 1:
The patent merges multiple power supply functions into a single shared power supply by introducing a delay unit that coordinates the timing of multiple clock signal outputs. This eliminates the need for separate power supplies for each clock signal while preventing waveform distortion through timing adjustment, thereby reducing device complexity and pin requirements
3Object-affected harmful factors
If regulators are built for each clock signal output, then output waveform distortion is improved, but the circuit area and cost increase
Solution Approach 1:
The patent extracts the waveform distortion problem from the power supply structure and addresses it separately through timing control. By removing the need for individual regulators and using a delay unit instead, the solution eliminates the additional circuit area and cost while still achieving the goal of reducing output waveform distortion
4Object-affected harmful factors
If clock signals are delayed to reduce power supply load, then output waveform distortion is reduced, but there is a risk of increasing delay variation
Solution Approach 1:
The patent applies parameter changes by carefully selecting and optimizing the predetermined delay time periods. The delay unit is designed with specific delay characteristics that spread out simultaneous switching events to reduce power supply load and waveform distortion, while the delay parameters are chosen to minimize any negative impact on delay variation and signal integrity
Data Source
AI summary
Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.