Voltage-Referenced Phase Rotator for Fine Clock Phase Interpolation

The patent extracts and eliminates the slew rate control circuitry from the phase rotator system. By using a voltage reference derived from a phase-locked loop (PLL) as the DAC reference voltage, the system removes the need for separate slew rate control mechanisms while maintaining phase interpolation accuracy. This is achieved by directly using the PLL output voltage to control the DAC, which in turn controls the phase output without requiring additional slew rate management circuits.

The patent applies multi-functionality by using the PLL circuit to serve dual purposes: frequency synthesis and voltage reference generation. The PLL's output voltage, which is already being used for frequency control, is simultaneously utilized as the reference voltage for the DAC. This eliminates the need for a separate voltage reference generation circuit, as the PLL performs both functions. The same PLL circuit that generates the clock frequency also provides the stable voltage reference needed for accurate phase control.

The patent employs feedback mechanisms through the PLL circuit to reduce sensitivity to clock signal variations. The PLL continuously monitors and adjusts its output to maintain phase lock, effectively filtering out variations in the input clock signal. By using the PLL's feedback-controlled voltage as the DAC reference, the system achieves accurate timing control while the PLL's inherent filtering properties reduce the impact of clock signal transition variations on the phase output.