Adaptive Column-Select Signal Generation for DRAM Timing
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face issues with insufficient pre-charge cycles and prolonged access times due to manufacturing variations and inappropriate parameter settings, leading to failures in write and read operations.
Innovation Solution
A method and circuit for adaptive column-select line signal generation, which involves generating a first signal in response to a memory access command and a second signal from candidate signals, allowing for configurable and specified time intervals to ensure a sufficient pre-charge cycle, thereby stabilizing access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed column-select line signal timing is used, then the circuit design is simple, but manufacturing variations and parameter settings cause insufficient pre-charge cycles and prolonged access times
Solution Approach 1:
The patent implements dynamic adjustment of the column-select line signal timing by introducing a controllable delay circuit that can modify the signal generation timing based on operational requirements. This allows the system to adapt to different access patterns and ensure sufficient pre-charge cycles while maintaining reliable operation.
Solution Approach 2:
The patent changes the timing parameter of the column-select line signal by allowing variable delay times through control signals. The delay circuit can adjust the timing based on configured parameters, enabling optimization of pre-charge cycles and access times under different operating conditions without fixing the timing rigidly.
2Reliability
If the column-select line signal timing is extended to ensure sufficient pre-charge cycle, then data line signal voltage reset is reliable, but access time is prolonged
Solution Approach 1:
The patent applies partial action by providing just enough delay to ensure reliable voltage reset without excessive extension of the access cycle. The controllable delay circuit is configured to add only the necessary timing margin, avoiding unnecessary time loss while maintaining sufficient pre-charge cycle for data line signal recovery.
Solution Approach 2:
The patent performs preliminary action by initiating the voltage reset process during the pre-charge cycle before the actual data access operation. The delayed column-select line signal is generated in advance to allow data line signals to be properly reset, ensuring readiness for subsequent operations without extending the overall access time unnecessarily.
3Adaptability or versatility
If configurable time interval is used for candidate signals, then adaptability to different operations is improved, but circuit complexity increases
Solution Approach 1:
The patent implements universality by designing a single controllable delay circuit that can serve multiple operation modes (read, write, pre-charge) through different control signals. The same delay mechanism adapts to various operational requirements by configuring different delay intervals, eliminating the need for separate timing circuits for each operation type.
Solution Approach 2:
The patent uses parameter changes by allowing the delay circuit to be configured with different time intervals based on operational mode. Control signals from the control logic adjust the delay parameter dynamically, enabling one circuit to handle multiple scenarios with varying timing requirements without adding significant complexity.
Data Source
AI summary
Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.