Digital Storage TRIZ Cases

Shared conductive tracks let memory cells across matrices support multi-row logic and direct data transfer without peripheral I/O circuits.

Embedded MTJ non-volatile and volatile memory cells cut FPGA startup transfer latency and energy by loading configuration bits locally.

Selective bypass switching lets critical memory signals avoid level shifter delay, improving access and input setup times across dual voltage rails.

A PVT-aware compensation circuit disables the bit line keeper when possible, cutting read 0 delay and extra current in single-ended memory.

Address-based word line pulse widths match bit-line RC characteristics, reducing memory read power without sacrificing accuracy.

Oxide semiconductor storage cells preserve logic connections after power-off while enabling fast reconfiguration with low leakage and power use.

Two RAM banks and a reconfigurable output module double data transfer rate without adding I/Os or pushing memory cores to higher read clocks.

A clock-gated capacitor uses the Miller feedback effect to raise critical charge in latch circuits, cutting radiation-induced soft errors with low area and power overhead.

An internal reference voltage and comparison path help a memory data receiver chip filter noise, improve read accuracy, and avoid extra pins.

Parallel color pipelines and clock-domain partitioning improve memory scheduling efficiency while preserving flexibility across memory protocols.

A four-switch RRAM shift circuit stores pre- and post-shift data in one memory element to cut circuit complexity, bandwidth demand, and power.

Non-volatile back-to-back resistive switches replace CRAM cells to improve read margins, cut standby current, and resist soft error upsets.

An integrated bit cell and multiplexer uses a PMOS pull-up to cut leakage, shrink area, and speed register file reads.

Delay-based phase mixing generates quadrature clocks in 1-2 cycles while keeping full input frequency and reducing phase error.

A built-in metastability detector checks critical latch voltages and gates downstream logic until a stable state is confirmed.

Memory multiplexing and arbitration let an AWG stream and update waveform data in real time without pausing output during testing.

A single resistive switching element gives an SRAM-like cell non-volatile retention while preserving fast access, low power use, and CMOS integration.

Repeated SRAM PUF startup checks flag unstable cells, helping quantify CMOS process variation without extra measurement hardware.

A metallization-layer write assist circuit holds digit-line voltage and boosts bitlines during writes to cut RC delay and reliability stress.

A resistive memory crossbar merges storage and arithmetic to cut data movement and support reconfigurable digital, analog, and neuromorphic computing.

Data concentration, spreading, and double-pumped clocks let DSP blocks run at 2x speed without costly redesign or added routing stress.

Multiphase internal clocks cut timing deviation in semiconductor memory while switching modes to avoid power-hungry correction circuits.

Incoming strobe timing drives the gating window, suppressing overhead edges while expanding receiver skew and timing drift tolerance.

Oversampling-based calibration corrects clock and strobe duty cycle distortion to align DDR timing windows across memory ranks.

A delayed precharge window suppresses premature discharge glitches in dynamic decode circuits, keeping outputs active longer and more stable.

Temperature-driven clock frequency control lets a DRAM pump circuit lower pump current at lower temperatures and cut unnecessary power use.

A delayed evaluate clock postpones precharge in dynamic decode circuits, reducing glitches and keeping outputs active longer.

Edge-triggered delay cells generate asynchronous clocks that remove ACTIVATE and PRECHARGE overhead in 2T2MTJ MRAM access.

Selective transceiver and I/O pad switching cuts unnecessary current and noise in multi-chip data links while preserving transfer speed.

Programmable RC delays tune clock and data paths to maintain memory hold margin across PVT corners with fewer delay logics and less area.

Fill-level status signals and phase-interpolated clock adjustment enable sub-cycle data buffer latency measurement without extra hardware.

Tailoring word line pulse widths to bit line RC length reduces memory read power while maintaining accurate read margins.

Earlier and later clock phases stabilize flip-flop input selection during scan readout, cutting hold-time violations, delay circuitry, and power use.

Split command paths and divided clocks give logic more time at high clock rates, preventing breakdown while maintaining throughput.

Level detection stops dynamic-node precharge below VDD and limits discharge near ground to cut power, leakage, and false logic detection.

Separate level shifters and tristated CMOS write drivers cut leakage and timing races while improving low-voltage memory writes.

Dynamic overdrive and underdrive of pass gate control boosts current drive during switching while cutting leakage in idle states.

A periodic single-wire signal lets a slave recover clock and data through delay paths, cutting pin count, power use, and speed limits.

Selectable buffers with matched delay paths offset timing skew, preserving setup and hold margins during semiconductor memory address capture.

Parallel SBR arrays let resistive memory correct failed bits in real time while avoiding the latency and space cost of replacement rows.