Double-Clocked DSP Blocks With Data Rate Conversion in ICs
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Solution Overview
Problem
Conventional programmable integrated circuits face challenges in improving performance due to the need for redesigning DSP blocks to operate at higher frequencies relative to other blocks, which is costly and complex, and introduces routing stress, reducing potential performance gains.
Innovation Solution
The integration of data rate concentration and spreading circuitry, along with clock generation circuitry, allows for double clocking of DSP blocks relative to other functional blocks, enabling efficient data transfer and operation at different data rates without increasing die area or cost, using multiplexers and registers synchronized by distinct clock pulse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DSP blocks are operated at higher frequencies relative to other blocks, then overall circuit performance is improved, but routing complexity and stress increase
Solution Approach 1:
The patent divides the clocking system into separate domains: a first clock signal for memory blocks and a second clock signal (at twice the frequency) for DSP blocks. This segmentation allows each block type to operate at its optimal frequency independently, improving overall circuit performance while avoiding the routing complexity that would arise from attempting to synchronize all blocks at a single high frequency.
2Speed
If DSP blocks are redesigned to operate at two times the frequency, then data transfer rate is improved, but manufacturing cost and implementation difficulty increase
Solution Approach 1:
The patent employs universal interface circuitry that can operate with both single-clock and double-clock configurations. The memory blocks and DSP blocks use standardized interfaces that are compatible with their respective clock domains, eliminating the need for custom redesigns while achieving doubled data transfer rates. This multi-functionality allows the same basic block designs to achieve different performance levels through clock configuration rather than structural redesign.
3Device complexity
If all blocks operate at the same clock frequency, then routing complexity is reduced, but overall performance is limited
Solution Approach 1:
The patent introduces clock conversion circuitry as an intermediary between the single-clock domain (memory blocks) and the double-clock domain (DSP blocks). This intermediary handles the frequency translation and synchronization, allowing blocks to operate at different frequencies without directly complicating the routing between them. The clock conversion layer absorbs the complexity of multi-frequency operation while presenting simplified interfaces to the functional blocks.
Data Source
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AI summary
An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion (130) of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion (120) of the functional blocks on the integrated circuit may operate at a 2x data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2x functional blocks, and data spreading circuitry at the output of the 2x functional blocks.