Bit Line Keeper Compensation for Faster Single-Ended Memory Reads
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Solution Overview
Problem
In memory devices with single-ended sensing, the bit line keeper circuit impacts memory access time due to higher leakage in CMOS technology nodes, particularly during read 0 operations, as it prevents the bit line from discharging below the switching threshold voltage of the sense inverter, affecting read 0 operation times.
Innovation Solution
A compensation circuit and switch configuration are introduced to control the bit line keeper, enabling its activation only when necessary, using a dummy signal to detect PVT variations and adjust the bit line keeper's operation, thereby minimizing its impact on memory access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line keeper circuit is introduced to prevent bit line discharge below the switching threshold voltage, then read 0 operation reliability is improved, but memory access time increases
Solution Approach 1:
The bit line keeper circuit is made dynamically controllable through a control signal that adjusts its operation based on detected PVT variations. The compensation circuit modifies the keeper circuit's activation state dynamically, allowing it to be disabled when not needed, thus reducing memory access time while maintaining reliability when leakage is high.
Solution Approach 2:
The invention changes the operational parameters of the bit line keeper circuit by introducing a control signal that adjusts its behavior based on detected process, voltage, and temperature conditions. This allows the keeper circuit to adapt its strength or activation state, optimizing the balance between reliability and access time under different operating conditions.
2Stability of the object's composition
If the bit line keeper circuit is activated to counteract leakage, then bit line voltage stability is improved, but extra current consumption increases
Solution Approach 1:
A compensation circuit is introduced that detects PVT variations and generates a control signal to adjust the bit line keeper circuit's operation. This feedback mechanism allows the system to activate or adjust the keeper circuit only when leakage conditions warrant it, thereby maintaining voltage stability while minimizing unnecessary current consumption during normal operation.
Solution Approach 2:
The bit line keeper circuit operation is adjusted periodically or conditionally based on detected PVT variations rather than remaining continuously active. The compensation circuit monitors conditions and modulates the keeper circuit's activation, creating a periodic or event-driven operation pattern that reduces average current consumption while maintaining voltage stability when needed.
3Reliability
If the bit line keeper circuit is kept active to handle leakage, then read 0 operation correctness is improved, but memory cycle time increases
Solution Approach 1:
The bit line keeper circuit transitions from a static always-on state to a dynamic state controlled by PVT detection. The compensation circuit enables the keeper circuit to be activated or deactivated based on real-time conditions, allowing the memory system to achieve correct read 0 operations only when leakage conditions require it, thereby reducing overall cycle time.
Data Source
AI summary
A circuit is disclosed that includes an inverter unit and a switch unit. The inverter unit is coupled to a memory cell column. The inverter unit is configured to invert, in response to a first control signal and a second control signal, a first signal and to output a second signal for the enabling or disabling of a bit line keeper circuit that is configured to maintain a bit line to a voltage. The first signal is generated by the memory cell column. The switch unit is configured to couple a reference voltage to an input of the inverter unit, in response to a third control signal. The inverter unit is further configured to be deactivated in response to the reference voltage, the first control signal, and the second control signal.