Multiphase Clock Generation for Low-Deviation Memory Timing
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in reducing timing deviations of clock signals, which can lead to erroneous operations, especially at higher frequencies, while also requiring reduced power consumption, as current correction circuits are complex and power-intensive.
Innovation Solution
A semiconductor device with a clock dividing circuit that provides internal clock signals with reduced timing deviation by operating in different modes, adjusting clock frequencies and phases, and using multiphase clock signals to generate strobe clock signals, allowing for lower power consumption by selecting between more accurate but power-hungry and less accurate clock signal configurations based on operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If correction circuits are used to adjust clock signal timing, then timing deviation is reduced, but power consumption increases significantly
Solution Approach 1:
The patent implements a dynamic clocking mechanism where the semiconductor device can operate in different modes: using external clock signals for write operations and internally generated clock signals for read operations. This dynamic switching allows the system to reduce power consumption by avoiding continuous use of power-intensive correction circuits while maintaining timing accuracy when needed.
Solution Approach 2:
The patent changes the clock signal generation parameters by switching between external and internal clock sources. The internal clock signals are generated by dividing the external clock frequency, creating multiple phases (e.g., 0°, 90°, 180°, 270°) that can be used for different operations. This parameter change allows timing deviation correction without continuously activating power-hungry correction circuits.
2Speed
If higher frequency clock signals are used for faster operation, then speed increases, but timing deviations increase causing erroneous operation
Solution Approach 1:
The patent segments the clock signal into multiple phases (e.g., four phases offset by 90 degrees each) generated through frequency division. This segmentation allows different phases to be used for different operations (write vs. read), enabling high-speed operation while maintaining timing accuracy through phase-specific timing relationships.
Solution Approach 2:
The patent introduces an intermediary clock dividing circuit that takes the external clock signal and generates multiple internal clock phases. This intermediary circuit acts as a buffer that maintains timing relationships while allowing the system to operate at higher frequencies without direct timing deviations affecting the core operations.
3Measurement precision
If complex correction circuits are implemented to reduce timing deviation, then timing accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements a self-service clocking system where the device generates its own internal clock signals by dividing the external clock frequency. This self-generated multi-phase clock system provides timing accuracy without requiring complex external correction circuits, as the timing relationships are inherently maintained through the division and phase generation process.
Data Source
AI summary
Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.