Shared-Track Memory Circuit for Multi-Row Logic Operations
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Solution Overview
Problem
Existing memory circuits face limitations in efficiently performing data transfers and calculation operations between separate storage areas, particularly in simultaneously accessing multiple rows of a matrix for logical operations and in efficiently interconnecting elementary cells across different matrices.
Innovation Solution
A memory circuit design with elementary cells having shared conductive tracks across matrices, allowing for simultaneous selection and operation of multiple rows, and incorporating additional transistors for read/write access ports and inverters, enabling efficient data transfer and calculation operations without requiring peripheral input/output circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If elementary cells are arranged in multiple matrices with shared conductive tracks, then data transfer efficiency between matrices is improved, but device complexity increases due to additional transistors and track interconnections
Solution Approach 1:
The patent merges multiple matrices by having elementary cells at the same coordinates in different matrices share the same first conductive track. This allows simultaneous access to multiple rows across matrices through a single track, improving data transfer efficiency while managing complexity through systematic sharing patterns
Solution Approach 2:
The first conductive track serves multiple functions by being shared across different matrices and supporting both read and write operations simultaneously. This multi-functionality reduces the total number of tracks needed, balancing the improvement in productivity against the increase in device complexity
2Speed
If multiple rows are simultaneously selected for reading operations, then calculation operation speed is improved, but manufacturing precision requirements increase due to simultaneous control of multiple transistors
Solution Approach 1:
The patent segments the memory into multiple independent matrices that can be simultaneously accessed. Each matrix can have its rows independently selected and read in parallel, enabling fast calculation operations while maintaining manageable control complexity through modular segmentation
Solution Approach 2:
The shared first conductive track acts as an intermediary that enables simultaneous read access to multiple rows across different matrices. This mediator allows parallel operations without requiring complex direct control of all transistors, reducing the manufacturing precision burden
3Device complexity
If peripheral input/output circuits are eliminated for direct data transfer, then device complexity is reduced, but reliability may worsen due to increased direct interconnections between storage areas
Solution Approach 1:
The memory circuit enables self-service data transfer between storage areas by allowing elementary cells to directly access and transfer data between matrices through shared conductive tracks. This eliminates the need for external peripheral I/O circuits, reducing device complexity while maintaining reliability through controlled direct access paths
Data Source
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AI summary
The invention relates to a memory circuit comprising a plurality of elementary cells (20) arranged in a plurality of matrices (Mi) each having several rows and several columns, and in which: the elementary cells (20) having the same coordinates in the different matrices (Mi) share the same first conductive track (VBLT); and in each matrix (Mi), the elementary cells (20) of the same row of the matrix share the same second conductive track (RWL) and the same third conductive track (WWL).