Resistive Memory Bit Repair Using Parallel SBR Bank Access
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Solution Overview
Problem
Conventional methods for handling bit failures in resistive memory devices, such as MRAM, are slow, inefficient, and unable to perform real-time repairs due to the need for multiple memory array accesses and high latency, leading to inaccuracies and limited capacity for dealing with failed rows or ports.
Innovation Solution
The implementation of a single bit repair (SBR) array, which is accessible in parallel with the resistive memory array, allows for real-time detection and correction of bit failures by storing failure indications at a bit level granularity, reducing storage needs and improving memory access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods using replacement rows and OTP NVM are used to handle bit failures, then failed bits can be detected and replaced, but memory access speed deteriorates due to multiple sequential accesses and high latency
Solution Approach 1:
The memory array is divided into multiple banks, with dedicated SBR arrays for each bank. This segmentation allows parallel access to different memory banks simultaneously, improving access speed while maintaining failure detection and correction capabilities across the entire memory array
Solution Approach 2:
SBR arrays are introduced as intermediary structures that store compact failure indication data. These SBR arrays act as mediators between the main memory banks and the control logic, enabling fast parallel lookup of failure information without requiring sequential access through OTP NVM or multiple memory accesses
2Reliability
If replacement rows are used to handle failed rows, then failed bits can be repaired, but memory space is consumed by redundant replacement row data
Solution Approach 1:
The failure indication information is extracted from the main memory array and stored separately in dedicated SBR arrays. This extraction allows the main memory space to be used efficiently for data storage while the SBR arrays use minimal space for compact failure metadata, significantly reducing the memory space overhead compared to storing entire replacement rows
Solution Approach 2:
Instead of creating full replacement rows as copies of failed rows, the invention creates compact copies of only the failure indication information in SBR arrays. This selective copying dramatically reduces the quantity of data that needs to be stored and managed while maintaining the ability to repair failed bits
3Reliability
If OTP NVM is used to store replacement row information, then failed rows can be tracked, but access time increases due to slow NVM access speed
Solution Approach 1:
The system dynamically adapts by using fast SRAM-based SBR arrays for storing failure indications in frequently accessed memory banks, while OTP NVM retains its role for less frequently accessed replacement information. This dynamic allocation optimizes access time for active memory operations while preserving the reliability of failed row tracking
Solution Approach 2:
Different storage media are assigned to different functional requirements: fast SRAM is used locally in each memory bank for immediate failure lookup, while slower OTP NVM is used for long-term storage of replacement information. This local quality differentiation optimizes both access speed for active operations and reliability for permanent record-keeping
Data Source
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AI summary
Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.