Dual-Bank Memory Output Circuit for Higher Data Rate I/O
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Solution Overview
Problem
Semiconductor integrated circuits, particularly island-style programmable logic devices, face challenges in increasing data transfer rates without expanding the area required for I/Os, as the data rate is limited by the maximum read clock frequency of memory cores and the number of I/Os.
Innovation Solution
The implementation of a configurable memory module with two RAM banks and a reconfigurable output module that can operate in both normal and double data rate modes, allowing simultaneous read operations from both banks in the double data rate mode to achieve a data transfer rate twice that of the normal mode without increasing the number of I/Os, by using a configurable decoder and multiplexers to manage address information and data selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of I/Os in the configurable block is increased to increase data bit width, then the data transfer rate is improved, but the area occupied by the configurable block increases significantly
Solution Approach 1:
The patent applies dynamics by making the output module reconfigurable between two operational modes (normal mode and double data rate mode). The output module can dynamically switch its function based on operational requirements, allowing the system to adapt its data output characteristics without physical reconfiguration of I/O connections.
Solution Approach 2:
The patent implements periodic action through double data rate mode where data is output at twice the clock frequency by alternating between two RAM banks. Data from BANK0 and BANK1 are sequentially selected and output in alternating clock cycles, effectively doubling the data transfer rate without requiring additional I/O pins.
2Productivity
If the maximum read clock frequency of the memory core is increased to improve data transfer rate, then the productivity is improved, but the reliability and stability may deteriorate due to timing constraints
Solution Approach 1:
The patent divides the memory system into two separate RAM banks (BANK0 and BANK1) with independent address counters and control logic. This segmentation allows each bank to operate independently at the original clock frequency, maintaining timing stability, while the combined output through sequential selection achieves doubled data transfer rate.
Solution Approach 2:
The patent introduces an intermediary output module that acts as a mediator between the two RAM banks and the external interface. This intermediary selectively outputs data from either BANK0 or BANK1 based on the current clock cycle, enabling rate doubling while isolating the memory cores from direct high-frequency timing constraints.
3Productivity
If the data width W is increased to improve data transfer rate, then the productivity is improved, but the number of I/Os required increases, occupying more area
Solution Approach 1:
The patent changes the operational parameters of the existing I/O interface by doubling the clock frequency instead of increasing data width. The same physical I/O connections are utilized, but the data transfer rate is doubled by transmitting data at twice the original clock speed through the reconfigurable output module.
Data Source
AI summary
A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in accordance with a first clock signal; a second memory bank performing a read operation and outputting second data in accordance with the first clock signal; a configurable decoder supplying address information to the first and second memory banks; and an output module reconfigurable in one of a first and second modes, the first mode including a function of holding the first and second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including a function of selecting and outputting the first data or the second data in accordance with the first clock signal.