Dynamic Decode Circuit With Delayed Precharge for Glitch Reduction
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Solution Overview
Problem
Dynamic decode circuits in dynamic logic face performance issues due to premature discharge of gates, leading to glitches and reduced efficiency, especially when cascading gates, as they consume precharge that cannot be restored until the next clock cycle.
Innovation Solution
The dynamic decode circuit is designed with a delayed precharge function that begins precharge a predetermined time after the evaluate period ends, and includes a special precharge circuit with a delayed evaluation clock signal to reduce the likelihood of unwanted glitches, allowing the output to remain active longer and improving performance by reducing transistor size and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precharge is performed immediately after evaluate phase, then circuit stability is improved, but output signal duration is reduced causing performance degradation
Solution Approach 1:
The patent applies preliminary action by performing the precharge operation before the evaluate phase completes. The precharge transistor is activated early in the clock cycle to charge the output node, and remains active during part of the evaluate phase. This allows the node to be precharged in advance while still maintaining the output signal for the required duration, resolving the contradiction between early precharge for stability and extended output duration for performance.
2Speed
If precharge transistor size is increased, then precharge speed is improved, but transistor area and circuit complexity increase
Solution Approach 1:
The patent applies dynamics by making the precharge transistor size variable rather than fixed. The effective size of the precharge transistor is dynamically controlled by the clock signal phase and duration. During early precharge, the full transistor capacity is utilized, but as the clock progresses, the transistor is gradually turned off, effectively reducing its size. This dynamic sizing allows fast precharge when needed while minimizing area occupation during other phases, resolving the contradiction between precharge speed and transistor area.
Data Source
AI summary
A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.