Memory Controller Color Pipelines for Flexible Scheduling
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Solution Overview
Problem
Conventional memory interface circuitry on programmable integrated circuits faces challenges in scaling across different memory protocols and topologies, with hardened solutions offering high performance but limited flexibility and soft solutions providing flexibility but compromised scheduling efficiency and performance.
Innovation Solution
The memory controller architecture is partitioned into memory protocol agnostic blocks, protocol dependent blocks, and user dependent blocks, with multiple color pipelines operating in parallel to process memory access requests, and a rate matching circuit for clock domain crossing, allowing for flexible configuration and improved scheduling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardened/fixed application-specific memory interface solutions are used, then operating frequency and performance are improved, but adaptability to different memory protocols and topologies deteriorates
Solution Approach 1:
The memory interface is divided into multiple color pipelines (e.g., first color pipeline, second color pipeline) that can independently process memory access requests. Each pipeline can be configured for different memory protocols and topologies, allowing the system to maintain high operating frequencies for specific applications while simultaneously supporting multiple memory protocol types through parallel pipeline operation.
2Adaptability or versatility
If soft/programmable memory interface solutions are used, then adaptability to different memory protocols is improved, but scheduling efficiency and performance deteriorate
Solution Approach 1:
The memory interface employs dynamic arbitration mechanisms including a color arbiter that selectively activates specific color pipelines based on the memory protocol being used. This dynamic configuration allows the system to optimize scheduling efficiency for each protocol type by enabling only the necessary pipelines, thereby maintaining high productivity while supporting protocol diversity.
3Productivity
If out-of-order memory processing is implemented, then memory bandwidth utilization is improved, but scheduling determinism deteriorates
Solution Approach 1:
The memory interface segments memory access requests into different color pipelines that can process requests out of order within each pipeline while maintaining overall system determinism through the color arbiter. This segmentation allows high bandwidth utilization through out-of-order processing while preserving scheduling determinism at the system level by coordinating pipeline execution.
Data Source
AI summary
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.