Quadra-Phase Clock Generator With Instant-On Delay Mixing
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Solution Overview
Problem
Conventional quadra-phase designs for generating clock signals require long initialization times and high power consumption, and often employ clock dividers that reduce the frequency and increase the period of multi-phase output signals.
Innovation Solution
A quadra-phase generator architecture that uses delay circuits to produce quadrature clock signals with minimal initialization time, achieving full input clock frequency over a wide operational bandwidth, by introducing a delay Δt that allows rising and falling edges of clock signals to align closely, thus reducing phase errors and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL with multiple adjustable delay lines or analog cells is used, then quadra-phase clock signals can be generated, but initialization time becomes long (spanning multiple clock cycles) and power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the delay elements to specific delay values before operation begins. The delay circuit is designed with predetermined delay settings that eliminate the need for runtime adjustment, allowing the system to achieve accurate phase relationships immediately upon startup without requiring multiple clock cycles for initialization.
2Measurement precision
If conventional PLL with multiple adjustable delay lines or analog cells is used, then quadra-phase clock signals can be generated, but power consumption becomes high
Solution Approach 1:
The patent employs a simplified delay circuit architecture that uses basic logic elements with predetermined delay characteristics rather than complex adjustable delay lines or analog cells. This approach uses simpler, lower-power components that achieve the required phase accuracy without the overhead of adjustable mechanisms, effectively replacing expensive complex components with cheaper simpler ones that suffice for the application.
3Measurement precision
If clock divider is used to generate multi-phase output signals, then phase offset of 90 degrees can be achieved, but frequency is halved and period is doubled
Solution Approach 1:
The patent changes the fundamental parameter approach from frequency division to delay-based phase generation. Instead of using a clock divider that reduces frequency to achieve phase offset, the system maintains the full input clock frequency and uses delay elements configured with specific delay values (Δt) to create the required phase relationships. This parameter change from division ratio to delay time enables both accurate phase offset and full frequency output.
Data Source
AI summary
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.