Single-Wire Interface Using Delayed Signal Sampling
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Solution Overview
Problem
Existing serial communication protocols like SPI and I2C require multiple pins for data and clock signals, increasing chip costs and power consumption, and have limited operating speeds due to their design.
Innovation Solution
A data processing system using a single wire interface where a master device generates a SPEEDY signal with both clock and data information, allowing a slave device to receive and process this signal using a delay circuit and processing circuit, reducing the number of pins needed and enabling low-power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple pins are used for data and clock signals (SPI/I2C), then communication functionality is achieved, but chip cost increases
Solution Approach 1:
The patent combines clock signal and data signal into a single wire interface. The master device generates a periodic signal where clock information and data information are multiplexed on the same transmission line, eliminating the need for separate clock and data pins used in traditional SPI or I2C interfaces.
Solution Approach 2:
The single wire interface serves multiple functions: it transmits both clock signals and data signals bidirectionally. The same physical connection is used for synchronization and information transfer, making the interface more versatile and reducing pin requirements.
2Use of energy by moving object
If multiple pins are used for data and clock signals, then communication functionality is achieved, but power consumption increases
Solution Approach 1:
The patent merges clock and data transmission into a single wire, reducing the number of active electrical connections. Fewer pins mean less capacitive loading and lower dynamic power consumption during signal transitions.
Solution Approach 2:
The communication uses periodic signaling where data is transmitted during specific phases of the clock cycle. This allows the system to enter low-power states between transmission periods, reducing overall power consumption compared to continuous multi-pin operation.
3Speed
If traditional serial buses (SPI/I2C) are used, then communication is achieved, but operating speed is limited
Solution Approach 1:
The master device prepares and transmits clock information in advance within the periodic signal structure. The slave device uses this pre-synchronized clock signal to timing its data sampling, enabling faster and more reliable data capture compared to traditional start-stop protocols.
Solution Approach 2:
The periodic signal acts as an intermediary that carries both synchronization (clock) and information (data) functions. This mediator enables the slave device to accurately time its operations without requiring separate clock wiring, thus increasing operating speed.
Data Source
AI summary
A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.